e2069a7b08
Gfx 9 starts to have multiple XCC instances in one device. Add instance parameter to kgd2kfd functions where XCC instance was hard coded as 0. Also, update code to pass the correct instance number when running on a multi-XCC setup. v2: introduce the XCC instance to gfx v11 (Morris) v3: rebase (Alex) Signed-off-by: Amber Lin <Amber.Lin@amd.com> Signed-off-by: Mukul Joshi <mukul.joshi@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Tested-by: Amber Lin <Amber.Lin@amd.com> Signed-off-by: Morris Zhang <Shiwu.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
66 lines
3.3 KiB
C
66 lines
3.3 KiB
C
/*
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* Copyright 2019 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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void kgd_gfx_v9_program_sh_mem_settings(struct amdgpu_device *adev, uint32_t vmid,
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uint32_t sh_mem_config,
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uint32_t sh_mem_ape1_base, uint32_t sh_mem_ape1_limit,
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uint32_t sh_mem_bases, uint32_t inst);
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int kgd_gfx_v9_set_pasid_vmid_mapping(struct amdgpu_device *adev, u32 pasid,
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unsigned int vmid, uint32_t inst);
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int kgd_gfx_v9_init_interrupts(struct amdgpu_device *adev, uint32_t pipe_id,
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uint32_t inst);
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int kgd_gfx_v9_hqd_load(struct amdgpu_device *adev, void *mqd, uint32_t pipe_id,
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uint32_t queue_id, uint32_t __user *wptr,
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uint32_t wptr_shift, uint32_t wptr_mask,
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struct mm_struct *mm, uint32_t inst);
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int kgd_gfx_v9_hiq_mqd_load(struct amdgpu_device *adev, void *mqd,
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uint32_t pipe_id, uint32_t queue_id,
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uint32_t doorbell_off, uint32_t inst);
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int kgd_gfx_v9_hqd_dump(struct amdgpu_device *adev,
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uint32_t pipe_id, uint32_t queue_id,
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uint32_t (**dump)[2], uint32_t *n_regs, uint32_t inst);
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bool kgd_gfx_v9_hqd_is_occupied(struct amdgpu_device *adev,
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uint64_t queue_address, uint32_t pipe_id,
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uint32_t queue_id, uint32_t inst);
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int kgd_gfx_v9_hqd_destroy(struct amdgpu_device *adev, void *mqd,
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enum kfd_preempt_type reset_type,
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unsigned int utimeout, uint32_t pipe_id,
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uint32_t queue_id, uint32_t inst);
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int kgd_gfx_v9_wave_control_execute(struct amdgpu_device *adev,
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uint32_t gfx_index_val,
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uint32_t sq_cmd, uint32_t inst);
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bool kgd_gfx_v9_get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev,
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uint8_t vmid, uint16_t *p_pasid);
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void kgd_gfx_v9_set_vm_context_page_table_base(struct amdgpu_device *adev,
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uint32_t vmid, uint64_t page_table_base);
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void kgd_gfx_v9_get_cu_occupancy(struct amdgpu_device *adev, int pasid,
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int *pasid_wave_cnt, int *max_waves_per_cu, uint32_t inst);
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void kgd_gfx_v9_program_trap_handler_settings(struct amdgpu_device *adev,
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uint32_t vmid, uint64_t tba_addr, uint64_t tma_addr,
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uint32_t inst);
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void kgd_gfx_v9_acquire_queue(struct amdgpu_device *adev, uint32_t pipe_id,
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uint32_t queue_id, uint32_t inst);
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uint64_t kgd_gfx_v9_get_queue_mask(struct amdgpu_device *adev,
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uint32_t pipe_id, uint32_t queue_id);
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void kgd_gfx_v9_release_queue(struct amdgpu_device *adev, uint32_t inst);
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