Alex Deucher f8646661f7 drm/amdgpu: fix up DCHUBBUB_SDPIF_MMIO_CNTRL_0 handling ... Properly define this register using a relative offset rather than an absolute offset and use the proper SOC15 macros to access it. It's also DCN, not DCE, so remove it from the DCE12 header. No functional change. Acked-by: Nirmoy Das <nirmoy.das@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2020-08-26 16:40:18 -04:00
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dce_6_0_d.h	drm/amdgpu: add some required DCE6 registers (v7)	2020-07-27 16:45:39 -04:00
dce_6_0_sh_mask.h	drm/amdgpu: add some required DCE6 registers (v7)	2020-07-27 16:45:39 -04:00
dce_8_0_d.h	drm/amd/amdgpu: Add DPHY_SCRAM_CNTL register defines	2017-01-27 11:12:44 -05:00
dce_8_0_enum.h	drm/amd: add dce8 enum register header	2016-02-10 14:17:02 -05:00
dce_8_0_sh_mask.h	drm/amd/amdgpu: Add DPHY_SCRAM_CNTL register defines	2017-01-27 11:12:44 -05:00
dce_10_0_d.h	drm/amd/amdgpu: Add DPHY_SCRAM_CNTL register defines	2017-01-27 11:12:44 -05:00
dce_10_0_enum.h	drm/amdgpu: add DCE 10.0 register headers	2015-06-03 21:02:53 -04:00
dce_10_0_sh_mask.h	drm/amd/amdgpu: Add DPHY_SCRAM_CNTL register defines	2017-01-27 11:12:44 -05:00
dce_11_0_d.h	drm/amd/amdgpu: Add DPHY_SCRAM_CNTL register defines	2017-01-27 11:12:44 -05:00
dce_11_0_enum.h	drm/amdgpu: add DCE 11.0 register headers	2015-06-03 21:02:54 -04:00
dce_11_0_sh_mask.h	drm/amd/amdgpu: Add DPHY_SCRAM_CNTL register defines	2017-01-27 11:12:44 -05:00
dce_11_2_d.h	drm/amd/amdgpu: Add DPHY_SCRAM_CNTL register defines	2017-01-27 11:12:44 -05:00
dce_11_2_enum.h	drm/amd: add DCE 11.2 register headers	2016-05-04 20:23:19 -04:00
dce_11_2_sh_mask.h	drm/amd/amdgpu: Add DPHY_SCRAM_CNTL register defines	2017-01-27 11:12:44 -05:00
dce_12_0_offset.h	drm/amdgpu: fix up DCHUBBUB_SDPIF_MMIO_CNTRL_0 handling	2020-08-26 16:40:18 -04:00
dce_12_0_sh_mask.h	drm/amd: Add dce-12.1 gpio aux registers (v2)	2018-05-17 10:13:19 -05:00