92cbbadf73
The LKGS instruction atomically loads a segment descriptor into the %gs descriptor registers, *except* that %gs.base is unchanged, and the base is instead loaded into MSR_IA32_KERNEL_GS_BASE, which is exactly what we want this function to do. Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com> Signed-off-by: Xin Li <xin3.li@intel.com> Signed-off-by: Ingo Molnar <mingo@kernel.org> Acked-by: Peter Zijlstra <peterz@infradead.org> Link: https://lore.kernel.org/r/20230112072032.35626-6-xin3.li@intel.com Cc: Andy Lutomirski <luto@kernel.org> Cc: Dave Hansen <dave.hansen@linux.intel.com> Cc: Linus Torvalds <torvalds@linux-foundation.org>
66 lines
1.4 KiB
C
66 lines
1.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef _ASM_X86_GSSEG_H
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#define _ASM_X86_GSSEG_H
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#include <linux/types.h>
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#include <asm/asm.h>
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#include <asm/cpufeature.h>
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#include <asm/alternative.h>
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#include <asm/processor.h>
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#include <asm/nops.h>
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#ifdef CONFIG_X86_64
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extern asmlinkage void asm_load_gs_index(u16 selector);
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/* Replace with "lkgs %di" once binutils support LKGS instruction */
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#define LKGS_DI _ASM_BYTES(0xf2,0x0f,0x00,0xf7)
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static inline void native_lkgs(unsigned int selector)
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{
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u16 sel = selector;
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asm_inline volatile("1: " LKGS_DI
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_ASM_EXTABLE_TYPE_REG(1b, 1b, EX_TYPE_ZERO_REG, %k[sel])
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: [sel] "+D" (sel));
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}
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static inline void native_load_gs_index(unsigned int selector)
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{
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if (cpu_feature_enabled(X86_FEATURE_LKGS)) {
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native_lkgs(selector);
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} else {
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unsigned long flags;
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local_irq_save(flags);
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asm_load_gs_index(selector);
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local_irq_restore(flags);
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}
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}
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#endif /* CONFIG_X86_64 */
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static inline void __init lkgs_init(void)
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{
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#ifdef CONFIG_PARAVIRT_XXL
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#ifdef CONFIG_X86_64
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if (cpu_feature_enabled(X86_FEATURE_LKGS))
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pv_ops.cpu.load_gs_index = native_lkgs;
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#endif
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#endif
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}
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#ifndef CONFIG_PARAVIRT_XXL
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static inline void load_gs_index(unsigned int selector)
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{
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#ifdef CONFIG_X86_64
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native_load_gs_index(selector);
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#else
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loadsegment(gs, selector);
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#endif
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}
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#endif /* CONFIG_PARAVIRT_XXL */
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#endif /* _ASM_X86_GSSEG_H */
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