docs: - lots of updated docs core: - require crtc to have unique primary plane - fourcc macro fix - PCI bar quirk for bar resizing - don't sent hotplug on error - move vm code to legacy - nuke hose only used on old oboslete alpha dma-buf: - kernel doc updates - improved lock tracking dp/hdmi: - DP-HDMI2.1 protocol converter support ttm: - bo size handling cleanup - release a pinned bo warning - cleanup lru handler - avoid using pages with drm_prime_sg_to_page_addr_arrays cma-helper: - prime/mmap fixes bridge: - add DP support gma500: - remove gma3600 support i915: - try eDP fast/narrow link again with fallback - Intel eDP backlight control - replace display register read/write macros - refactor intel_display.c - display power improvements - HPD code cleanup - Rocketlake display fixes - Power/backlight/RPM fixes - DG1 display fix - IVB/BYT clear residuals security fix again - make i915 mitigations options via parameter - HSW GT1 GPU hangs fixes - DG1 workaround hang fixes - TGL DMAR hang avoidance - Lots of GT fixes - follow on fixes for residuals clear - gen7 per-engine-reset support - HDCP2.2 + HDCP1.4 GEN12 DP MST support - TGL clear color support - backlight refactoring - VRR/Adaptive sync enabling on DP/EDP for TGL+ - async flips for all ilk+ amdgpu: - rework IH ring handling (Vega/Navi) - rework HDP handling (Vega/Navi) - swSMU updates for renoir/vangogh - Sienna Cichild overdrive support - FP16 on DCE8-11 support - GPU reset on navy flounder/vangogh - SMU profile fixes for APU - SR-IOV fixes - Vangogh SMU fixes - fan speed control fixes amdkfd: - config handling fix - buffer free fix - recursive lock warnings fix nouveau: - Turing MMU fault recovery fixes - mDP connectors reporting fix - audio locking fixes - rework engines/instances code to support new scheme tegra: - VIC newer firmware support - display/gr2d fixes for older tegra - pm reference leak fix mediatek: - SOC MT8183 support - decouple sub driver + share mtk mutex driver radeon: - PCI resource fix for some platforms ingenic: - pm support - 8-bit delta RGB panels vmwgfx: - managed driver helpers vc4: - BCM2711 DSI1 support - converted to atomic helpers - enable 10/12 bpc outputs - gem prime mmap helpers - CEC fix omap: - use degamma table - CTM support - rework DSI support imx: - stack usage fixes - drm managed support - imx-tve clock provider leak fix - rcar-du: - default mode fixes - conversion to managed API hisilicon: - use simple encoder vkms: - writeback connector support d3: - BT2020 support -----BEGIN PGP SIGNATURE----- iQIcBAABAgAGBQJgL1RCAAoJEAx081l5xIa+BxoP/325goULPaGBwUKgVkSl6mTT Ror0r8U3ifQHrqPk57C5b4GfvNuJ8vJZC13GYiiwooPn/+sifbl8haMRQWKyH4fz PThm9vroIQZ8VC+fqixgrOwFKEwkKqucZ3f7dEj8paBVVcO9DcBIaSeO4QW2EAR/ n2r7nHtFxVHYEwiOnJvIeWIh1dAmudr/U6pHyB6PnuofVgqveXHT5+mmkY51pJqF sn2Y+Ye3tP5+FDlKkueg8JUteyFRTGz1g7JQThxSI//b/+p4MmmRX03qcWvIIkOX XiNlP73Ssh7PPMcUgwFmvKbMfm9sfpwf7yX3nqzaAQAHZGufznxX0k50BRkxWyYL eMVxRs5/Vl5JAn3vhspAUZhc4BgOcJm9L4zazb7YqDghwpohSnXk/riunUevqFCf Dgsc8N63nft8WEBk3aB6loRpDDpo5rm8gVpl5LKk1YXT92o9x4eP+/B1+kf2RepM 52H3CKD1GLK3ayJlRNa/ljE2qXaQru+PmjCxORgDPEZ7SXdb8q5bfH0MjCB4vEBp YIybWYIDQzRBKglN5qMQ3XNIgv95oqrxXKaDFFtp8lMEjVG0v+y2antzFHftXS2g Cj0aeyBx4PC3pNbZe54npEhFwVIs7NFXX9brpQnnLJvQj/Qp+GEhf8uqiCUJNnYA AF7qRRL0bBGTeiJGt4nM =TeKl -----END PGP SIGNATURE----- Merge tag 'drm-next-2021-02-19' of git://anongit.freedesktop.org/drm/drm Pull drm updates from Dave Airlie: "A pretty normal tree, lots of refactoring across the board, ttm, i915, nouveau, and bunch of features in various drivers. docs: - lots of updated docs core: - require crtc to have unique primary plane - fourcc macro fix - PCI bar quirk for bar resizing - don't sent hotplug on error - move vm code to legacy - nuke hose only used on old oboslete alpha dma-buf: - kernel doc updates - improved lock tracking dp/hdmi: - DP-HDMI2.1 protocol converter support ttm: - bo size handling cleanup - release a pinned bo warning - cleanup lru handler - avoid using pages with drm_prime_sg_to_page_addr_arrays cma-helper: - prime/mmap fixes bridge: - add DP support gma500: - remove gma3600 support i915: - try eDP fast/narrow link again with fallback - Intel eDP backlight control - replace display register read/write macros - refactor intel_display.c - display power improvements - HPD code cleanup - Rocketlake display fixes - Power/backlight/RPM fixes - DG1 display fix - IVB/BYT clear residuals security fix again - make i915 mitigations options via parameter - HSW GT1 GPU hangs fixes - DG1 workaround hang fixes - TGL DMAR hang avoidance - Lots of GT fixes - follow on fixes for residuals clear - gen7 per-engine-reset support - HDCP2.2 + HDCP1.4 GEN12 DP MST support - TGL clear color support - backlight refactoring - VRR/Adaptive sync enabling on DP/EDP for TGL+ - async flips for all ilk+ amdgpu: - rework IH ring handling (Vega/Navi) - rework HDP handling (Vega/Navi) - swSMU updates for renoir/vangogh - Sienna Cichild overdrive support - FP16 on DCE8-11 support - GPU reset on navy flounder/vangogh - SMU profile fixes for APU - SR-IOV fixes - Vangogh SMU fixes - fan speed control fixes amdkfd: - config handling fix - buffer free fix - recursive lock warnings fix nouveau: - Turing MMU fault recovery fixes - mDP connectors reporting fix - audio locking fixes - rework engines/instances code to support new scheme tegra: - VIC newer firmware support - display/gr2d fixes for older tegra - pm reference leak fix mediatek: - SOC MT8183 support - decouple sub driver + share mtk mutex driver radeon: - PCI resource fix for some platforms ingenic: - pm support - 8-bit delta RGB panels vmwgfx: - managed driver helpers vc4: - BCM2711 DSI1 support - converted to atomic helpers - enable 10/12 bpc outputs - gem prime mmap helpers - CEC fix omap: - use degamma table - CTM support - rework DSI support imx: - stack usage fixes - drm managed support - imx-tve clock provider leak fix - rcar-du: - default mode fixes - conversion to managed API hisilicon: - use simple encoder vkms: - writeback connector support d3: - BT2020 support" * tag 'drm-next-2021-02-19' of git://anongit.freedesktop.org/drm/drm: (1459 commits) drm/amdgpu: Set reference clock to 100Mhz on Renoir (v2) drm/radeon: OLAND boards don't have VCE drm/amdkfd: Fix recursive lock warnings drm/amd/display: Add FPU wrappers to dcn21_validate_bandwidth() drm/amd/display: Fix potential integer overflow drm/amdgpu/display: remove hdcp_srm sysfs on device removal drm/amdgpu: fix CGTS_TCC_DISABLE register offset on gfx10.3 drm/i915/gt: Correct surface base address for renderclear drm/i915: Disallow plane x+w>stride on ilk+ with X-tiling drm/nouveau/top/ga100: initial support drm/nouveau/top: add ioctrl/nvjpg drm/nouveau/privring: rename from ibus drm/nouveau/nvkm: remove nvkm_subdev.index drm/nouveau/nvkm: determine subdev id/order from layout drm/nouveau/vic: switch to instanced constructor drm/nouveau/sw: switch to instanced constructor drm/nouveau/sec2: switch to instanced constructor drm/nouveau/sec: switch to instanced constructor drm/nouveau/pm: switch to instanced constructor drm/nouveau/nvenc: switch to instanced constructor ...
462 lines
11 KiB
C
462 lines
11 KiB
C
/*
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* Copyright 2008 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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* Copyright 2009 Jerome Glisse.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Dave Airlie
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* Alex Deucher
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* Jerome Glisse
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*/
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#include "amdgpu.h"
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#include "atom.h"
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#include <linux/pci.h>
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#include <linux/slab.h>
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#include <linux/acpi.h>
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/*
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* BIOS.
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*/
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#define AMD_VBIOS_SIGNATURE " 761295520"
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#define AMD_VBIOS_SIGNATURE_OFFSET 0x30
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#define AMD_VBIOS_SIGNATURE_SIZE sizeof(AMD_VBIOS_SIGNATURE)
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#define AMD_VBIOS_SIGNATURE_END (AMD_VBIOS_SIGNATURE_OFFSET + AMD_VBIOS_SIGNATURE_SIZE)
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#define AMD_IS_VALID_VBIOS(p) ((p)[0] == 0x55 && (p)[1] == 0xAA)
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#define AMD_VBIOS_LENGTH(p) ((p)[2] << 9)
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/* Check if current bios is an ATOM BIOS.
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* Return true if it is ATOM BIOS. Otherwise, return false.
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*/
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static bool check_atom_bios(uint8_t *bios, size_t size)
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{
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uint16_t tmp, bios_header_start;
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if (!bios || size < 0x49) {
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DRM_INFO("vbios mem is null or mem size is wrong\n");
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return false;
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}
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if (!AMD_IS_VALID_VBIOS(bios)) {
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DRM_INFO("BIOS signature incorrect %x %x\n", bios[0], bios[1]);
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return false;
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}
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bios_header_start = bios[0x48] | (bios[0x49] << 8);
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if (!bios_header_start) {
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DRM_INFO("Can't locate bios header\n");
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return false;
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}
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tmp = bios_header_start + 4;
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if (size < tmp) {
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DRM_INFO("BIOS header is broken\n");
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return false;
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}
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if (!memcmp(bios + tmp, "ATOM", 4) ||
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!memcmp(bios + tmp, "MOTA", 4)) {
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DRM_DEBUG("ATOMBIOS detected\n");
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return true;
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}
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return false;
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}
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/* If you boot an IGP board with a discrete card as the primary,
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* the IGP rom is not accessible via the rom bar as the IGP rom is
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* part of the system bios. On boot, the system bios puts a
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* copy of the igp rom at the start of vram if a discrete card is
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* present.
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*/
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static bool igp_read_bios_from_vram(struct amdgpu_device *adev)
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{
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uint8_t __iomem *bios;
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resource_size_t vram_base;
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resource_size_t size = 256 * 1024; /* ??? */
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if (!(adev->flags & AMD_IS_APU))
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if (amdgpu_device_need_post(adev))
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return false;
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adev->bios = NULL;
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vram_base = pci_resource_start(adev->pdev, 0);
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bios = ioremap_wc(vram_base, size);
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if (!bios) {
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return false;
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}
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adev->bios = kmalloc(size, GFP_KERNEL);
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if (!adev->bios) {
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iounmap(bios);
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return false;
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}
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adev->bios_size = size;
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memcpy_fromio(adev->bios, bios, size);
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iounmap(bios);
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if (!check_atom_bios(adev->bios, size)) {
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kfree(adev->bios);
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return false;
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}
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return true;
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}
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bool amdgpu_read_bios(struct amdgpu_device *adev)
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{
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uint8_t __iomem *bios;
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size_t size;
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adev->bios = NULL;
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/* XXX: some cards may return 0 for rom size? ddx has a workaround */
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bios = pci_map_rom(adev->pdev, &size);
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if (!bios) {
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return false;
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}
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adev->bios = kzalloc(size, GFP_KERNEL);
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if (adev->bios == NULL) {
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pci_unmap_rom(adev->pdev, bios);
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return false;
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}
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adev->bios_size = size;
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memcpy_fromio(adev->bios, bios, size);
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pci_unmap_rom(adev->pdev, bios);
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if (!check_atom_bios(adev->bios, size)) {
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kfree(adev->bios);
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return false;
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}
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return true;
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}
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static bool amdgpu_read_bios_from_rom(struct amdgpu_device *adev)
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{
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u8 header[AMD_VBIOS_SIGNATURE_END+1] = {0};
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int len;
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if (!adev->asic_funcs || !adev->asic_funcs->read_bios_from_rom)
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return false;
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/* validate VBIOS signature */
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if (amdgpu_asic_read_bios_from_rom(adev, &header[0], sizeof(header)) == false)
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return false;
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header[AMD_VBIOS_SIGNATURE_END] = 0;
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if ((!AMD_IS_VALID_VBIOS(header)) ||
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0 != memcmp((char *)&header[AMD_VBIOS_SIGNATURE_OFFSET],
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AMD_VBIOS_SIGNATURE,
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strlen(AMD_VBIOS_SIGNATURE)))
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return false;
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/* valid vbios, go on */
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len = AMD_VBIOS_LENGTH(header);
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len = ALIGN(len, 4);
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adev->bios = kmalloc(len, GFP_KERNEL);
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if (!adev->bios) {
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DRM_ERROR("no memory to allocate for BIOS\n");
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return false;
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}
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adev->bios_size = len;
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/* read complete BIOS */
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amdgpu_asic_read_bios_from_rom(adev, adev->bios, len);
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if (!check_atom_bios(adev->bios, len)) {
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kfree(adev->bios);
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return false;
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}
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return true;
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}
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static bool amdgpu_read_platform_bios(struct amdgpu_device *adev)
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{
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phys_addr_t rom = adev->pdev->rom;
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size_t romlen = adev->pdev->romlen;
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void __iomem *bios;
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adev->bios = NULL;
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if (!rom || romlen == 0)
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return false;
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adev->bios = kzalloc(romlen, GFP_KERNEL);
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if (!adev->bios)
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return false;
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bios = ioremap(rom, romlen);
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if (!bios)
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goto free_bios;
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memcpy_fromio(adev->bios, bios, romlen);
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iounmap(bios);
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if (!check_atom_bios(adev->bios, romlen))
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goto free_bios;
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adev->bios_size = romlen;
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return true;
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free_bios:
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kfree(adev->bios);
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return false;
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}
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#ifdef CONFIG_ACPI
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/* ATRM is used to get the BIOS on the discrete cards in
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* dual-gpu systems.
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*/
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/* retrieve the ROM in 4k blocks */
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#define ATRM_BIOS_PAGE 4096
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/**
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* amdgpu_atrm_call - fetch a chunk of the vbios
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*
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* @atrm_handle: acpi ATRM handle
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* @bios: vbios image pointer
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* @offset: offset of vbios image data to fetch
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* @len: length of vbios image data to fetch
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*
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* Executes ATRM to fetch a chunk of the discrete
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* vbios image on PX systems (all asics).
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* Returns the length of the buffer fetched.
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*/
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static int amdgpu_atrm_call(acpi_handle atrm_handle, uint8_t *bios,
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int offset, int len)
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{
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acpi_status status;
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union acpi_object atrm_arg_elements[2], *obj;
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struct acpi_object_list atrm_arg;
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struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL};
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atrm_arg.count = 2;
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atrm_arg.pointer = &atrm_arg_elements[0];
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atrm_arg_elements[0].type = ACPI_TYPE_INTEGER;
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atrm_arg_elements[0].integer.value = offset;
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atrm_arg_elements[1].type = ACPI_TYPE_INTEGER;
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atrm_arg_elements[1].integer.value = len;
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status = acpi_evaluate_object(atrm_handle, NULL, &atrm_arg, &buffer);
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if (ACPI_FAILURE(status)) {
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printk("failed to evaluate ATRM got %s\n", acpi_format_exception(status));
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return -ENODEV;
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}
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obj = (union acpi_object *)buffer.pointer;
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memcpy(bios+offset, obj->buffer.pointer, obj->buffer.length);
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len = obj->buffer.length;
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kfree(buffer.pointer);
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return len;
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}
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static bool amdgpu_atrm_get_bios(struct amdgpu_device *adev)
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{
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int ret;
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int size = 256 * 1024;
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int i;
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struct pci_dev *pdev = NULL;
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acpi_handle dhandle, atrm_handle;
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acpi_status status;
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bool found = false;
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/* ATRM is for the discrete card only */
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if (adev->flags & AMD_IS_APU)
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return false;
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while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) {
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dhandle = ACPI_HANDLE(&pdev->dev);
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if (!dhandle)
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continue;
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status = acpi_get_handle(dhandle, "ATRM", &atrm_handle);
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if (ACPI_SUCCESS(status)) {
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found = true;
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break;
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}
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}
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if (!found) {
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while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) {
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dhandle = ACPI_HANDLE(&pdev->dev);
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if (!dhandle)
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continue;
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status = acpi_get_handle(dhandle, "ATRM", &atrm_handle);
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if (ACPI_SUCCESS(status)) {
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found = true;
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break;
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}
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}
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}
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if (!found)
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return false;
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adev->bios = kmalloc(size, GFP_KERNEL);
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if (!adev->bios) {
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DRM_ERROR("Unable to allocate bios\n");
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return false;
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}
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for (i = 0; i < size / ATRM_BIOS_PAGE; i++) {
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ret = amdgpu_atrm_call(atrm_handle,
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adev->bios,
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(i * ATRM_BIOS_PAGE),
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ATRM_BIOS_PAGE);
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if (ret < ATRM_BIOS_PAGE)
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break;
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}
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if (!check_atom_bios(adev->bios, size)) {
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kfree(adev->bios);
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return false;
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}
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adev->bios_size = size;
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return true;
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}
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#else
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static inline bool amdgpu_atrm_get_bios(struct amdgpu_device *adev)
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{
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return false;
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}
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#endif
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static bool amdgpu_read_disabled_bios(struct amdgpu_device *adev)
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{
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if (adev->flags & AMD_IS_APU)
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return igp_read_bios_from_vram(adev);
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else
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return (!adev->asic_funcs || !adev->asic_funcs->read_disabled_bios) ?
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false : amdgpu_asic_read_disabled_bios(adev);
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}
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#ifdef CONFIG_ACPI
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static bool amdgpu_acpi_vfct_bios(struct amdgpu_device *adev)
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{
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struct acpi_table_header *hdr;
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acpi_size tbl_size;
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UEFI_ACPI_VFCT *vfct;
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unsigned offset;
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if (!ACPI_SUCCESS(acpi_get_table("VFCT", 1, &hdr)))
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return false;
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tbl_size = hdr->length;
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if (tbl_size < sizeof(UEFI_ACPI_VFCT)) {
|
|
DRM_ERROR("ACPI VFCT table present but broken (too short #1)\n");
|
|
return false;
|
|
}
|
|
|
|
vfct = (UEFI_ACPI_VFCT *)hdr;
|
|
offset = vfct->VBIOSImageOffset;
|
|
|
|
while (offset < tbl_size) {
|
|
GOP_VBIOS_CONTENT *vbios = (GOP_VBIOS_CONTENT *)((char *)hdr + offset);
|
|
VFCT_IMAGE_HEADER *vhdr = &vbios->VbiosHeader;
|
|
|
|
offset += sizeof(VFCT_IMAGE_HEADER);
|
|
if (offset > tbl_size) {
|
|
DRM_ERROR("ACPI VFCT image header truncated\n");
|
|
return false;
|
|
}
|
|
|
|
offset += vhdr->ImageLength;
|
|
if (offset > tbl_size) {
|
|
DRM_ERROR("ACPI VFCT image truncated\n");
|
|
return false;
|
|
}
|
|
|
|
if (vhdr->ImageLength &&
|
|
vhdr->PCIBus == adev->pdev->bus->number &&
|
|
vhdr->PCIDevice == PCI_SLOT(adev->pdev->devfn) &&
|
|
vhdr->PCIFunction == PCI_FUNC(adev->pdev->devfn) &&
|
|
vhdr->VendorID == adev->pdev->vendor &&
|
|
vhdr->DeviceID == adev->pdev->device) {
|
|
adev->bios = kmemdup(&vbios->VbiosContent,
|
|
vhdr->ImageLength,
|
|
GFP_KERNEL);
|
|
|
|
if (!check_atom_bios(adev->bios, vhdr->ImageLength)) {
|
|
kfree(adev->bios);
|
|
return false;
|
|
}
|
|
adev->bios_size = vhdr->ImageLength;
|
|
return true;
|
|
}
|
|
}
|
|
|
|
DRM_ERROR("ACPI VFCT table present but broken (too short #2)\n");
|
|
return false;
|
|
}
|
|
#else
|
|
static inline bool amdgpu_acpi_vfct_bios(struct amdgpu_device *adev)
|
|
{
|
|
return false;
|
|
}
|
|
#endif
|
|
|
|
bool amdgpu_get_bios(struct amdgpu_device *adev)
|
|
{
|
|
if (amdgpu_atrm_get_bios(adev)) {
|
|
dev_info(adev->dev, "Fetched VBIOS from ATRM\n");
|
|
goto success;
|
|
}
|
|
|
|
if (amdgpu_acpi_vfct_bios(adev)) {
|
|
dev_info(adev->dev, "Fetched VBIOS from VFCT\n");
|
|
goto success;
|
|
}
|
|
|
|
if (igp_read_bios_from_vram(adev)) {
|
|
dev_info(adev->dev, "Fetched VBIOS from VRAM BAR\n");
|
|
goto success;
|
|
}
|
|
|
|
if (amdgpu_read_bios(adev)) {
|
|
dev_info(adev->dev, "Fetched VBIOS from ROM BAR\n");
|
|
goto success;
|
|
}
|
|
|
|
if (amdgpu_read_bios_from_rom(adev)) {
|
|
dev_info(adev->dev, "Fetched VBIOS from ROM\n");
|
|
goto success;
|
|
}
|
|
|
|
if (amdgpu_read_disabled_bios(adev)) {
|
|
dev_info(adev->dev, "Fetched VBIOS from disabled ROM BAR\n");
|
|
goto success;
|
|
}
|
|
|
|
if (amdgpu_read_platform_bios(adev)) {
|
|
dev_info(adev->dev, "Fetched VBIOS from platform\n");
|
|
goto success;
|
|
}
|
|
|
|
DRM_ERROR("Unable to locate a BIOS ROM\n");
|
|
return false;
|
|
|
|
success:
|
|
adev->is_atom_fw = (adev->asic_type >= CHIP_VEGA10) ? true : false;
|
|
return true;
|
|
}
|