Alex Deucher c241ed2f0e drm/amdgpu/display: drop DCN support for aarch64 ... From Ard: "Simply disabling -mgeneral-regs-only left and right is risky, given that the standard AArch64 ABI permits the use of FP/SIMD registers anywhere, and GCC is known to use SIMD registers for spilling, and may invent other uses of the FP/SIMD register file that have nothing to do with the floating point code in question. Note that putting kernel_neon_begin() and kernel_neon_end() around the code that does use FP is not sufficient here, the problem is in all the other code that may be emitted with references to SIMD registers in it. So the only way to do this properly is to put all floating point code in a separate compilation unit, and only compile that unit with -mgeneral-regs-only." Disable support until the code can be properly refactored to support this properly on aarch64. Acked-by: Will Deacon <will@kernel.org> Reported-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2021-01-06 16:24:10 -05:00
..
dc_dsc.c	drm/amd/display: Add an option to limit max DSC target bpp per sink	2020-10-26 13:29:39 -04:00
dscc_types.h	drm/amd/display: Drop CONFIG_DRM_AMD_DC_DCN2_0 and DSC_SUPPORTED	2019-11-13 15:29:44 -05:00
Makefile	drm/amdgpu/display: drop DCN support for aarch64	2021-01-06 16:24:10 -05:00
qp_tables.h	drm/amd/display: Drop CONFIG_DRM_AMD_DC_DCN2_0 and DSC_SUPPORTED	2019-11-13 15:29:44 -05:00
rc_calc.c	drm/amd/display: Fix compilation error	2020-11-02 15:29:33 -05:00
rc_calc.h	drm/amd/display: Fix compilation error	2020-11-02 15:29:33 -05:00
rc_calc_dpi.c	drm/amd/display: Rework dsc to isolate FPU operations	2020-07-01 01:59:20 -04:00