[Why & How] On DCN1.0, need otg vertical line interrupt to get appropriate timing to achieve specific feature request. Add otg vertical interrupt0 support for registers which operation is vertical sensitive. Signed-off-by: Wayne Lin <Wayne.Lin@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> |
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dce60 | ||
dce80 | ||
dce110 | ||
dce120 | ||
dcn10 | ||
dcn20 | ||
dcn21 | ||
dcn30 | ||
dcn302 | ||
irq_service.c | ||
irq_service.h | ||
Makefile |