ae07970a06
Implement hwmon API for reading/setting slow and fast PPT limit.
APU power is managed to system-level requirements through the PPT
(package power tracking) feature. PPT is intended to limit power to the
requirements of the power source and could be dynamically updated to
maximize APU performance within the system power budget.
Here FAST_PPT_LIMIT manages the ~10 ms moving average of APU power,
while SLOW_PPT_LIMIT manages the configurable, thermally significant
moving average of APU power (default ~5000 ms).
User could read slow/fast ppt limit using command "cat power*_cap" or
"sensors" in the hwmon device directory. User could adjust values of
slow/fast ppt limit as needed depending on workloads through command
"echo ## > power*_cap".
Example:
$ echo 15000000 > power1_cap
$ echo 18000000 > power2_cap
$ sensors
amdgpu-pci-0300
Adapter: PCI adapter
slowPPT: 9.04W (cap = 15.00 W)
fastPPT: 9.04W (cap = 18.00 W)
v2: align with existing interfaces for the getting/setting of PPT
limits. Encode the upper 8 bits of limit value to distinguish
slow and fast power limit type.
Signed-off-by: Xiaomeng Hou <Xiaomeng.Hou@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
1356 lines
38 KiB
C
1356 lines
38 KiB
C
/*
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* Copyright 2019 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef __AMDGPU_SMU_H__
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#define __AMDGPU_SMU_H__
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#include "amdgpu.h"
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#include "kgd_pp_interface.h"
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#include "dm_pp_interface.h"
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#include "dm_pp_smu.h"
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#include "smu_types.h"
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#define SMU_THERMAL_MINIMUM_ALERT_TEMP 0
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#define SMU_THERMAL_MAXIMUM_ALERT_TEMP 255
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#define SMU_TEMPERATURE_UNITS_PER_CENTIGRADES 1000
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#define SMU_FW_NAME_LEN 0x24
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#define SMU_DPM_USER_PROFILE_RESTORE (1 << 0)
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struct smu_hw_power_state {
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unsigned int magic;
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};
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struct smu_power_state;
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enum smu_state_ui_label {
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SMU_STATE_UI_LABEL_NONE,
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SMU_STATE_UI_LABEL_BATTERY,
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SMU_STATE_UI_TABEL_MIDDLE_LOW,
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SMU_STATE_UI_LABEL_BALLANCED,
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SMU_STATE_UI_LABEL_MIDDLE_HIGHT,
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SMU_STATE_UI_LABEL_PERFORMANCE,
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SMU_STATE_UI_LABEL_BACO,
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};
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enum smu_state_classification_flag {
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SMU_STATE_CLASSIFICATION_FLAG_BOOT = 0x0001,
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SMU_STATE_CLASSIFICATION_FLAG_THERMAL = 0x0002,
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SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE = 0x0004,
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SMU_STATE_CLASSIFICATION_FLAG_RESET = 0x0008,
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SMU_STATE_CLASSIFICATION_FLAG_FORCED = 0x0010,
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SMU_STATE_CLASSIFICATION_FLAG_USER_3D_PERFORMANCE = 0x0020,
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SMU_STATE_CLASSIFICATION_FLAG_USER_2D_PERFORMANCE = 0x0040,
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SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE = 0x0080,
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SMU_STATE_CLASSIFICATION_FLAG_AC_OVERDIRVER_TEMPLATE = 0x0100,
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SMU_STATE_CLASSIFICATION_FLAG_UVD = 0x0200,
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SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE_LOW = 0x0400,
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SMU_STATE_CLASSIFICATION_FLAG_ACPI = 0x0800,
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SMU_STATE_CLASSIFICATION_FLAG_HD2 = 0x1000,
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SMU_STATE_CLASSIFICATION_FLAG_UVD_HD = 0x2000,
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SMU_STATE_CLASSIFICATION_FLAG_UVD_SD = 0x4000,
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SMU_STATE_CLASSIFICATION_FLAG_USER_DC_PERFORMANCE = 0x8000,
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SMU_STATE_CLASSIFICATION_FLAG_DC_OVERDIRVER_TEMPLATE = 0x10000,
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SMU_STATE_CLASSIFICATION_FLAG_BACO = 0x20000,
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SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE2 = 0x40000,
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SMU_STATE_CLASSIFICATION_FLAG_ULV = 0x80000,
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SMU_STATE_CLASSIFICATION_FLAG_UVD_MVC = 0x100000,
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};
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struct smu_state_classification_block {
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enum smu_state_ui_label ui_label;
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enum smu_state_classification_flag flags;
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int bios_index;
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bool temporary_state;
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bool to_be_deleted;
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};
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struct smu_state_pcie_block {
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unsigned int lanes;
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};
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enum smu_refreshrate_source {
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SMU_REFRESHRATE_SOURCE_EDID,
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SMU_REFRESHRATE_SOURCE_EXPLICIT
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};
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struct smu_state_display_block {
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bool disable_frame_modulation;
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bool limit_refreshrate;
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enum smu_refreshrate_source refreshrate_source;
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int explicit_refreshrate;
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int edid_refreshrate_index;
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bool enable_vari_bright;
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};
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struct smu_state_memory_block {
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bool dll_off;
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uint8_t m3arb;
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uint8_t unused[3];
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};
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struct smu_state_software_algorithm_block {
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bool disable_load_balancing;
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bool enable_sleep_for_timestamps;
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};
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struct smu_temperature_range {
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int min;
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int max;
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int edge_emergency_max;
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int hotspot_min;
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int hotspot_crit_max;
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int hotspot_emergency_max;
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int mem_min;
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int mem_crit_max;
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int mem_emergency_max;
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int software_shutdown_temp;
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};
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struct smu_state_validation_block {
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bool single_display_only;
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bool disallow_on_dc;
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uint8_t supported_power_levels;
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};
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struct smu_uvd_clocks {
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uint32_t vclk;
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uint32_t dclk;
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};
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/**
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* Structure to hold a SMU Power State.
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*/
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struct smu_power_state {
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uint32_t id;
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struct list_head ordered_list;
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struct list_head all_states_list;
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struct smu_state_classification_block classification;
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struct smu_state_validation_block validation;
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struct smu_state_pcie_block pcie;
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struct smu_state_display_block display;
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struct smu_state_memory_block memory;
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struct smu_state_software_algorithm_block software;
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struct smu_uvd_clocks uvd_clocks;
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struct smu_hw_power_state hardware;
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};
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enum smu_power_src_type
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{
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SMU_POWER_SOURCE_AC,
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SMU_POWER_SOURCE_DC,
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SMU_POWER_SOURCE_COUNT,
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};
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enum smu_ppt_limit_type
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{
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SMU_DEFAULT_PPT_LIMIT = 0,
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SMU_FAST_PPT_LIMIT,
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};
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enum smu_ppt_limit_level
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{
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SMU_PPT_LIMIT_MIN = -1,
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SMU_PPT_LIMIT_CURRENT,
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SMU_PPT_LIMIT_MAX,
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};
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enum smu_memory_pool_size
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{
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SMU_MEMORY_POOL_SIZE_ZERO = 0,
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SMU_MEMORY_POOL_SIZE_256_MB = 0x10000000,
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SMU_MEMORY_POOL_SIZE_512_MB = 0x20000000,
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SMU_MEMORY_POOL_SIZE_1_GB = 0x40000000,
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SMU_MEMORY_POOL_SIZE_2_GB = 0x80000000,
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};
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struct smu_user_dpm_profile {
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uint32_t fan_mode;
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uint32_t power_limit;
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uint32_t fan_speed_percent;
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uint32_t flags;
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/* user clock state information */
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uint32_t clk_mask[SMU_CLK_COUNT];
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uint32_t clk_dependency;
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};
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#define SMU_TABLE_INIT(tables, table_id, s, a, d) \
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do { \
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tables[table_id].size = s; \
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tables[table_id].align = a; \
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tables[table_id].domain = d; \
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} while (0)
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struct smu_table {
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uint64_t size;
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uint32_t align;
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uint8_t domain;
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uint64_t mc_address;
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void *cpu_addr;
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struct amdgpu_bo *bo;
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};
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enum smu_perf_level_designation {
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PERF_LEVEL_ACTIVITY,
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PERF_LEVEL_POWER_CONTAINMENT,
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};
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struct smu_performance_level {
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uint32_t core_clock;
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uint32_t memory_clock;
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uint32_t vddc;
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uint32_t vddci;
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uint32_t non_local_mem_freq;
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uint32_t non_local_mem_width;
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};
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struct smu_clock_info {
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uint32_t min_mem_clk;
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uint32_t max_mem_clk;
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uint32_t min_eng_clk;
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uint32_t max_eng_clk;
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uint32_t min_bus_bandwidth;
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uint32_t max_bus_bandwidth;
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};
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struct smu_bios_boot_up_values
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{
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uint32_t revision;
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uint32_t gfxclk;
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uint32_t uclk;
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uint32_t socclk;
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uint32_t dcefclk;
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uint32_t eclk;
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uint32_t vclk;
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uint32_t dclk;
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uint16_t vddc;
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uint16_t vddci;
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uint16_t mvddc;
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uint16_t vdd_gfx;
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uint8_t cooling_id;
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uint32_t pp_table_id;
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uint32_t format_revision;
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uint32_t content_revision;
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uint32_t fclk;
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uint32_t lclk;
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uint32_t firmware_caps;
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};
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enum smu_table_id
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{
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SMU_TABLE_PPTABLE = 0,
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SMU_TABLE_WATERMARKS,
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SMU_TABLE_CUSTOM_DPM,
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SMU_TABLE_DPMCLOCKS,
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SMU_TABLE_AVFS,
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SMU_TABLE_AVFS_PSM_DEBUG,
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SMU_TABLE_AVFS_FUSE_OVERRIDE,
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SMU_TABLE_PMSTATUSLOG,
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SMU_TABLE_SMU_METRICS,
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SMU_TABLE_DRIVER_SMU_CONFIG,
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SMU_TABLE_ACTIVITY_MONITOR_COEFF,
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SMU_TABLE_OVERDRIVE,
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SMU_TABLE_I2C_COMMANDS,
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SMU_TABLE_PACE,
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SMU_TABLE_COUNT,
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};
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struct smu_table_context
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{
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void *power_play_table;
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uint32_t power_play_table_size;
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void *hardcode_pptable;
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unsigned long metrics_time;
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void *metrics_table;
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void *clocks_table;
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void *watermarks_table;
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void *max_sustainable_clocks;
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struct smu_bios_boot_up_values boot_values;
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void *driver_pptable;
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struct smu_table tables[SMU_TABLE_COUNT];
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/*
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* The driver table is just a staging buffer for
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* uploading/downloading content from the SMU.
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*
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* And the table_id for SMU_MSG_TransferTableSmu2Dram/
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* SMU_MSG_TransferTableDram2Smu instructs SMU
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* which content driver is interested.
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*/
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struct smu_table driver_table;
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struct smu_table memory_pool;
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struct smu_table dummy_read_1_table;
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uint8_t thermal_controller_type;
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void *overdrive_table;
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void *boot_overdrive_table;
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uint32_t gpu_metrics_table_size;
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void *gpu_metrics_table;
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};
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struct smu_dpm_context {
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uint32_t dpm_context_size;
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void *dpm_context;
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void *golden_dpm_context;
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bool enable_umd_pstate;
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enum amd_dpm_forced_level dpm_level;
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enum amd_dpm_forced_level saved_dpm_level;
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enum amd_dpm_forced_level requested_dpm_level;
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struct smu_power_state *dpm_request_power_state;
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struct smu_power_state *dpm_current_power_state;
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struct mclock_latency_table *mclk_latency_table;
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};
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struct smu_power_gate {
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bool uvd_gated;
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bool vce_gated;
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atomic_t vcn_gated;
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atomic_t jpeg_gated;
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struct mutex vcn_gate_lock;
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struct mutex jpeg_gate_lock;
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};
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struct smu_power_context {
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void *power_context;
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uint32_t power_context_size;
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struct smu_power_gate power_gate;
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};
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#define SMU_FEATURE_MAX (64)
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struct smu_feature
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{
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uint32_t feature_num;
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DECLARE_BITMAP(supported, SMU_FEATURE_MAX);
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DECLARE_BITMAP(allowed, SMU_FEATURE_MAX);
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DECLARE_BITMAP(enabled, SMU_FEATURE_MAX);
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struct mutex mutex;
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};
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struct smu_clocks {
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uint32_t engine_clock;
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uint32_t memory_clock;
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uint32_t bus_bandwidth;
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uint32_t engine_clock_in_sr;
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uint32_t dcef_clock;
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uint32_t dcef_clock_in_sr;
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};
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#define MAX_REGULAR_DPM_NUM 16
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struct mclk_latency_entries {
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uint32_t frequency;
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uint32_t latency;
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};
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struct mclock_latency_table {
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uint32_t count;
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struct mclk_latency_entries entries[MAX_REGULAR_DPM_NUM];
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};
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enum smu_reset_mode
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{
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SMU_RESET_MODE_0,
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SMU_RESET_MODE_1,
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SMU_RESET_MODE_2,
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};
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enum smu_baco_state
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{
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SMU_BACO_STATE_ENTER = 0,
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SMU_BACO_STATE_EXIT,
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};
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struct smu_baco_context
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{
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struct mutex mutex;
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uint32_t state;
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bool platform_support;
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};
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struct pstates_clk_freq {
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uint32_t min;
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uint32_t standard;
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uint32_t peak;
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};
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struct smu_umd_pstate_table {
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struct pstates_clk_freq gfxclk_pstate;
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struct pstates_clk_freq socclk_pstate;
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struct pstates_clk_freq uclk_pstate;
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struct pstates_clk_freq vclk_pstate;
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struct pstates_clk_freq dclk_pstate;
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};
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struct cmn2asic_msg_mapping {
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int valid_mapping;
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int map_to;
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int valid_in_vf;
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};
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struct cmn2asic_mapping {
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int valid_mapping;
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int map_to;
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};
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#define WORKLOAD_POLICY_MAX 7
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struct smu_context
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{
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struct amdgpu_device *adev;
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struct amdgpu_irq_src irq_source;
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const struct pptable_funcs *ppt_funcs;
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const struct cmn2asic_msg_mapping *message_map;
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const struct cmn2asic_mapping *clock_map;
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const struct cmn2asic_mapping *feature_map;
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const struct cmn2asic_mapping *table_map;
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const struct cmn2asic_mapping *pwr_src_map;
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const struct cmn2asic_mapping *workload_map;
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struct mutex mutex;
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struct mutex sensor_lock;
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struct mutex metrics_lock;
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struct mutex message_lock;
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uint64_t pool_size;
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struct smu_table_context smu_table;
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struct smu_dpm_context smu_dpm;
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struct smu_power_context smu_power;
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struct smu_feature smu_feature;
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struct amd_pp_display_configuration *display_config;
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struct smu_baco_context smu_baco;
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struct smu_temperature_range thermal_range;
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void *od_settings;
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#if defined(CONFIG_DEBUG_FS)
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struct dentry *debugfs_sclk;
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#endif
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struct smu_umd_pstate_table pstate_table;
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uint32_t pstate_sclk;
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uint32_t pstate_mclk;
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bool od_enabled;
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uint32_t current_power_limit;
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uint32_t max_power_limit;
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/* soft pptable */
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uint32_t ppt_offset_bytes;
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uint32_t ppt_size_bytes;
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uint8_t *ppt_start_addr;
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bool support_power_containment;
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bool disable_watermark;
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#define WATERMARKS_EXIST (1 << 0)
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#define WATERMARKS_LOADED (1 << 1)
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uint32_t watermarks_bitmap;
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uint32_t hard_min_uclk_req_from_dal;
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bool disable_uclk_switch;
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uint32_t workload_mask;
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uint32_t workload_prority[WORKLOAD_POLICY_MAX];
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uint32_t workload_setting[WORKLOAD_POLICY_MAX];
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uint32_t power_profile_mode;
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uint32_t default_power_profile_mode;
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bool pm_enabled;
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bool is_apu;
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uint32_t smc_driver_if_version;
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uint32_t smc_fw_if_version;
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uint32_t smc_fw_version;
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bool uploading_custom_pp_table;
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bool dc_controlled_by_gpio;
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struct work_struct throttling_logging_work;
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|
atomic64_t throttle_int_counter;
|
|
struct work_struct interrupt_work;
|
|
|
|
unsigned fan_max_rpm;
|
|
unsigned manual_fan_speed_percent;
|
|
|
|
uint32_t gfx_default_hard_min_freq;
|
|
uint32_t gfx_default_soft_max_freq;
|
|
uint32_t gfx_actual_hard_min_freq;
|
|
uint32_t gfx_actual_soft_max_freq;
|
|
|
|
/* APU only */
|
|
uint32_t cpu_default_soft_min_freq;
|
|
uint32_t cpu_default_soft_max_freq;
|
|
uint32_t cpu_actual_soft_min_freq;
|
|
uint32_t cpu_actual_soft_max_freq;
|
|
uint32_t cpu_core_id_select;
|
|
uint16_t cpu_core_num;
|
|
|
|
struct smu_user_dpm_profile user_dpm_profile;
|
|
};
|
|
|
|
struct i2c_adapter;
|
|
|
|
/**
|
|
* struct pptable_funcs - Callbacks used to interact with the SMU.
|
|
*/
|
|
struct pptable_funcs {
|
|
/**
|
|
* @run_btc: Calibrate voltage/frequency curve to fit the system's
|
|
* power delivery and voltage margins. Required for adaptive
|
|
* voltage frequency scaling (AVFS).
|
|
*/
|
|
int (*run_btc)(struct smu_context *smu);
|
|
|
|
/**
|
|
* @get_allowed_feature_mask: Get allowed feature mask.
|
|
* &feature_mask: Array to store feature mask.
|
|
* &num: Elements in &feature_mask.
|
|
*/
|
|
int (*get_allowed_feature_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);
|
|
|
|
/**
|
|
* @get_current_power_state: Get the current power state.
|
|
*
|
|
* Return: Current power state on success, negative errno on failure.
|
|
*/
|
|
enum amd_pm_state_type (*get_current_power_state)(struct smu_context *smu);
|
|
|
|
/**
|
|
* @set_default_dpm_table: Retrieve the default overdrive settings from
|
|
* the SMU.
|
|
*/
|
|
int (*set_default_dpm_table)(struct smu_context *smu);
|
|
|
|
int (*set_power_state)(struct smu_context *smu);
|
|
|
|
/**
|
|
* @populate_umd_state_clk: Populate the UMD power state table with
|
|
* defaults.
|
|
*/
|
|
int (*populate_umd_state_clk)(struct smu_context *smu);
|
|
|
|
/**
|
|
* @print_clk_levels: Print DPM clock levels for a clock domain
|
|
* to buffer. Star current level.
|
|
*
|
|
* Used for sysfs interfaces.
|
|
*/
|
|
int (*print_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, char *buf);
|
|
|
|
/**
|
|
* @force_clk_levels: Set a range of allowed DPM levels for a clock
|
|
* domain.
|
|
* &clk_type: Clock domain.
|
|
* &mask: Range of allowed DPM levels.
|
|
*/
|
|
int (*force_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t mask);
|
|
|
|
/**
|
|
* @od_edit_dpm_table: Edit the custom overdrive DPM table.
|
|
* &type: Type of edit.
|
|
* &input: Edit parameters.
|
|
* &size: Size of &input.
|
|
*/
|
|
int (*od_edit_dpm_table)(struct smu_context *smu,
|
|
enum PP_OD_DPM_TABLE_COMMAND type,
|
|
long *input, uint32_t size);
|
|
|
|
/**
|
|
* @get_clock_by_type_with_latency: Get the speed and latency of a clock
|
|
* domain.
|
|
*/
|
|
int (*get_clock_by_type_with_latency)(struct smu_context *smu,
|
|
enum smu_clk_type clk_type,
|
|
struct
|
|
pp_clock_levels_with_latency
|
|
*clocks);
|
|
/**
|
|
* @get_clock_by_type_with_voltage: Get the speed and voltage of a clock
|
|
* domain.
|
|
*/
|
|
int (*get_clock_by_type_with_voltage)(struct smu_context *smu,
|
|
enum amd_pp_clock_type type,
|
|
struct
|
|
pp_clock_levels_with_voltage
|
|
*clocks);
|
|
|
|
/**
|
|
* @get_power_profile_mode: Print all power profile modes to
|
|
* buffer. Star current mode.
|
|
*/
|
|
int (*get_power_profile_mode)(struct smu_context *smu, char *buf);
|
|
|
|
/**
|
|
* @set_power_profile_mode: Set a power profile mode. Also used to
|
|
* create/set custom power profile modes.
|
|
* &input: Power profile mode parameters.
|
|
* &size: Size of &input.
|
|
*/
|
|
int (*set_power_profile_mode)(struct smu_context *smu, long *input, uint32_t size);
|
|
|
|
/**
|
|
* @dpm_set_vcn_enable: Enable/disable VCN engine dynamic power
|
|
* management.
|
|
*/
|
|
int (*dpm_set_vcn_enable)(struct smu_context *smu, bool enable);
|
|
|
|
/**
|
|
* @dpm_set_jpeg_enable: Enable/disable JPEG engine dynamic power
|
|
* management.
|
|
*/
|
|
int (*dpm_set_jpeg_enable)(struct smu_context *smu, bool enable);
|
|
|
|
/**
|
|
* @read_sensor: Read data from a sensor.
|
|
* &sensor: Sensor to read data from.
|
|
* &data: Sensor reading.
|
|
* &size: Size of &data.
|
|
*/
|
|
int (*read_sensor)(struct smu_context *smu, enum amd_pp_sensors sensor,
|
|
void *data, uint32_t *size);
|
|
|
|
/**
|
|
* @pre_display_config_changed: Prepare GPU for a display configuration
|
|
* change.
|
|
*
|
|
* Disable display tracking and pin memory clock speed to maximum. Used
|
|
* in display component synchronization.
|
|
*/
|
|
int (*pre_display_config_changed)(struct smu_context *smu);
|
|
|
|
/**
|
|
* @display_config_changed: Notify the SMU of the current display
|
|
* configuration.
|
|
*
|
|
* Allows SMU to properly track blanking periods for memory clock
|
|
* adjustment. Used in display component synchronization.
|
|
*/
|
|
int (*display_config_changed)(struct smu_context *smu);
|
|
|
|
int (*apply_clocks_adjust_rules)(struct smu_context *smu);
|
|
|
|
/**
|
|
* @notify_smc_display_config: Applies display requirements to the
|
|
* current power state.
|
|
*
|
|
* Optimize deep sleep DCEFclk and mclk for the current display
|
|
* configuration. Used in display component synchronization.
|
|
*/
|
|
int (*notify_smc_display_config)(struct smu_context *smu);
|
|
|
|
/**
|
|
* @is_dpm_running: Check if DPM is running.
|
|
*
|
|
* Return: True if DPM is running, false otherwise.
|
|
*/
|
|
bool (*is_dpm_running)(struct smu_context *smu);
|
|
|
|
/**
|
|
* @get_fan_speed_percent: Get the current fan speed in percent.
|
|
*/
|
|
int (*get_fan_speed_percent)(struct smu_context *smu, uint32_t *speed);
|
|
|
|
/**
|
|
* @set_watermarks_table: Configure and upload the watermarks tables to
|
|
* the SMU.
|
|
*/
|
|
int (*set_watermarks_table)(struct smu_context *smu,
|
|
struct pp_smu_wm_range_sets *clock_ranges);
|
|
|
|
/**
|
|
* @get_thermal_temperature_range: Get safe thermal limits in Celcius.
|
|
*/
|
|
int (*get_thermal_temperature_range)(struct smu_context *smu, struct smu_temperature_range *range);
|
|
|
|
/**
|
|
* @get_uclk_dpm_states: Get memory clock DPM levels in kHz.
|
|
* &clocks_in_khz: Array of DPM levels.
|
|
* &num_states: Elements in &clocks_in_khz.
|
|
*/
|
|
int (*get_uclk_dpm_states)(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states);
|
|
|
|
/**
|
|
* @set_default_od_settings: Set the overdrive tables to defaults.
|
|
*/
|
|
int (*set_default_od_settings)(struct smu_context *smu);
|
|
|
|
/**
|
|
* @set_performance_level: Set a performance level.
|
|
*/
|
|
int (*set_performance_level)(struct smu_context *smu, enum amd_dpm_forced_level level);
|
|
|
|
/**
|
|
* @display_disable_memory_clock_switch: Enable/disable dynamic memory
|
|
* clock switching.
|
|
*
|
|
* Disabling this feature forces memory clock speed to maximum.
|
|
* Enabling sets the minimum memory clock capable of driving the
|
|
* current display configuration.
|
|
*/
|
|
int (*display_disable_memory_clock_switch)(struct smu_context *smu, bool disable_memory_clock_switch);
|
|
|
|
/**
|
|
* @dump_pptable: Print the power play table to the system log.
|
|
*/
|
|
void (*dump_pptable)(struct smu_context *smu);
|
|
|
|
/**
|
|
* @get_power_limit: Get the device's power limits.
|
|
*/
|
|
int (*get_power_limit)(struct smu_context *smu);
|
|
|
|
/**
|
|
* @get_ppt_limit: Get the device's ppt limits.
|
|
*/
|
|
int (*get_ppt_limit)(struct smu_context *smu, uint32_t *ppt_limit,
|
|
enum smu_ppt_limit_type limit_type, enum smu_ppt_limit_level limit_level);
|
|
|
|
/**
|
|
* @set_df_cstate: Set data fabric cstate.
|
|
*/
|
|
int (*set_df_cstate)(struct smu_context *smu, enum pp_df_cstate state);
|
|
|
|
/**
|
|
* @allow_xgmi_power_down: Enable/disable external global memory
|
|
* interconnect power down.
|
|
*/
|
|
int (*allow_xgmi_power_down)(struct smu_context *smu, bool en);
|
|
|
|
/**
|
|
* @update_pcie_parameters: Update and upload the system's PCIe
|
|
* capabilites to the SMU.
|
|
* &pcie_gen_cap: Maximum allowed PCIe generation.
|
|
* &pcie_width_cap: Maximum allowed PCIe width.
|
|
*/
|
|
int (*update_pcie_parameters)(struct smu_context *smu, uint32_t pcie_gen_cap, uint32_t pcie_width_cap);
|
|
|
|
/**
|
|
* @i2c_init: Initialize i2c.
|
|
*
|
|
* The i2c bus is used internally by the SMU voltage regulators and
|
|
* other devices. The i2c's EEPROM also stores bad page tables on boards
|
|
* with ECC.
|
|
*/
|
|
int (*i2c_init)(struct smu_context *smu, struct i2c_adapter *control);
|
|
|
|
/**
|
|
* @i2c_fini: Tear down i2c.
|
|
*/
|
|
void (*i2c_fini)(struct smu_context *smu, struct i2c_adapter *control);
|
|
|
|
/**
|
|
* @get_unique_id: Get the GPU's unique id. Used for asset tracking.
|
|
*/
|
|
void (*get_unique_id)(struct smu_context *smu);
|
|
|
|
/**
|
|
* @get_dpm_clock_table: Get a copy of the DPM clock table.
|
|
*
|
|
* Used by display component in bandwidth and watermark calculations.
|
|
*/
|
|
int (*get_dpm_clock_table)(struct smu_context *smu, struct dpm_clocks *clock_table);
|
|
|
|
/**
|
|
* @init_microcode: Request the SMU's firmware from the kernel.
|
|
*/
|
|
int (*init_microcode)(struct smu_context *smu);
|
|
|
|
/**
|
|
* @load_microcode: Load firmware onto the SMU.
|
|
*/
|
|
int (*load_microcode)(struct smu_context *smu);
|
|
|
|
/**
|
|
* @fini_microcode: Release the SMU's firmware.
|
|
*/
|
|
void (*fini_microcode)(struct smu_context *smu);
|
|
|
|
/**
|
|
* @init_smc_tables: Initialize the SMU tables.
|
|
*/
|
|
int (*init_smc_tables)(struct smu_context *smu);
|
|
|
|
/**
|
|
* @fini_smc_tables: Release the SMU tables.
|
|
*/
|
|
int (*fini_smc_tables)(struct smu_context *smu);
|
|
|
|
/**
|
|
* @init_power: Initialize the power gate table context.
|
|
*/
|
|
int (*init_power)(struct smu_context *smu);
|
|
|
|
/**
|
|
* @fini_power: Release the power gate table context.
|
|
*/
|
|
int (*fini_power)(struct smu_context *smu);
|
|
|
|
/**
|
|
* @check_fw_status: Check the SMU's firmware status.
|
|
*
|
|
* Return: Zero if check passes, negative errno on failure.
|
|
*/
|
|
int (*check_fw_status)(struct smu_context *smu);
|
|
|
|
/**
|
|
* @setup_pptable: Initialize the power play table and populate it with
|
|
* default values.
|
|
*/
|
|
int (*setup_pptable)(struct smu_context *smu);
|
|
|
|
/**
|
|
* @get_vbios_bootup_values: Get default boot values from the VBIOS.
|
|
*/
|
|
int (*get_vbios_bootup_values)(struct smu_context *smu);
|
|
|
|
/**
|
|
* @check_fw_version: Print driver and SMU interface versions to the
|
|
* system log.
|
|
*
|
|
* Interface mismatch is not a critical failure.
|
|
*/
|
|
int (*check_fw_version)(struct smu_context *smu);
|
|
|
|
/**
|
|
* @powergate_sdma: Power up/down system direct memory access.
|
|
*/
|
|
int (*powergate_sdma)(struct smu_context *smu, bool gate);
|
|
|
|
/**
|
|
* @set_gfx_cgpg: Enable/disable graphics engine course grain power
|
|
* gating.
|
|
*/
|
|
int (*set_gfx_cgpg)(struct smu_context *smu, bool enable);
|
|
|
|
/**
|
|
* @write_pptable: Write the power play table to the SMU.
|
|
*/
|
|
int (*write_pptable)(struct smu_context *smu);
|
|
|
|
/**
|
|
* @set_driver_table_location: Send the location of the driver table to
|
|
* the SMU.
|
|
*/
|
|
int (*set_driver_table_location)(struct smu_context *smu);
|
|
|
|
/**
|
|
* @set_tool_table_location: Send the location of the tool table to the
|
|
* SMU.
|
|
*/
|
|
int (*set_tool_table_location)(struct smu_context *smu);
|
|
|
|
/**
|
|
* @notify_memory_pool_location: Send the location of the memory pool to
|
|
* the SMU.
|
|
*/
|
|
int (*notify_memory_pool_location)(struct smu_context *smu);
|
|
|
|
/**
|
|
* @system_features_control: Enable/disable all SMU features.
|
|
*/
|
|
int (*system_features_control)(struct smu_context *smu, bool en);
|
|
|
|
/**
|
|
* @send_smc_msg_with_param: Send a message with a parameter to the SMU.
|
|
* &msg: Type of message.
|
|
* ¶m: Message parameter.
|
|
* &read_arg: SMU response (optional).
|
|
*/
|
|
int (*send_smc_msg_with_param)(struct smu_context *smu,
|
|
enum smu_message_type msg, uint32_t param, uint32_t *read_arg);
|
|
|
|
/**
|
|
* @send_smc_msg: Send a message to the SMU.
|
|
* &msg: Type of message.
|
|
* &read_arg: SMU response (optional).
|
|
*/
|
|
int (*send_smc_msg)(struct smu_context *smu,
|
|
enum smu_message_type msg,
|
|
uint32_t *read_arg);
|
|
|
|
/**
|
|
* @init_display_count: Notify the SMU of the number of display
|
|
* components in current display configuration.
|
|
*/
|
|
int (*init_display_count)(struct smu_context *smu, uint32_t count);
|
|
|
|
/**
|
|
* @set_allowed_mask: Notify the SMU of the features currently allowed
|
|
* by the driver.
|
|
*/
|
|
int (*set_allowed_mask)(struct smu_context *smu);
|
|
|
|
/**
|
|
* @get_enabled_mask: Get a mask of features that are currently enabled
|
|
* on the SMU.
|
|
* &feature_mask: Array representing enabled feature mask.
|
|
* &num: Elements in &feature_mask.
|
|
*/
|
|
int (*get_enabled_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);
|
|
|
|
/**
|
|
* @feature_is_enabled: Test if a feature is enabled.
|
|
*
|
|
* Return: One if enabled, zero if disabled.
|
|
*/
|
|
int (*feature_is_enabled)(struct smu_context *smu, enum smu_feature_mask mask);
|
|
|
|
/**
|
|
* @disable_all_features_with_exception: Disable all features with
|
|
* exception to those in &mask.
|
|
*/
|
|
int (*disable_all_features_with_exception)(struct smu_context *smu, enum smu_feature_mask mask);
|
|
|
|
/**
|
|
* @notify_display_change: Enable fast memory clock switching.
|
|
*
|
|
* Allows for fine grained memory clock switching but has more stringent
|
|
* timing requirements.
|
|
*/
|
|
int (*notify_display_change)(struct smu_context *smu);
|
|
|
|
/**
|
|
* @set_power_limit: Set power limit in watts.
|
|
*/
|
|
int (*set_power_limit)(struct smu_context *smu, uint32_t n);
|
|
|
|
/**
|
|
* @init_max_sustainable_clocks: Populate max sustainable clock speed
|
|
* table with values from the SMU.
|
|
*/
|
|
int (*init_max_sustainable_clocks)(struct smu_context *smu);
|
|
|
|
/**
|
|
* @enable_thermal_alert: Enable thermal alert interrupts.
|
|
*/
|
|
int (*enable_thermal_alert)(struct smu_context *smu);
|
|
|
|
/**
|
|
* @disable_thermal_alert: Disable thermal alert interrupts.
|
|
*/
|
|
int (*disable_thermal_alert)(struct smu_context *smu);
|
|
|
|
/**
|
|
* @set_min_dcef_deep_sleep: Set a minimum display fabric deep sleep
|
|
* clock speed in MHz.
|
|
*/
|
|
int (*set_min_dcef_deep_sleep)(struct smu_context *smu, uint32_t clk);
|
|
|
|
/**
|
|
* @display_clock_voltage_request: Set a hard minimum frequency
|
|
* for a clock domain.
|
|
*/
|
|
int (*display_clock_voltage_request)(struct smu_context *smu, struct
|
|
pp_display_clock_request
|
|
*clock_req);
|
|
|
|
/**
|
|
* @get_fan_control_mode: Get the current fan control mode.
|
|
*/
|
|
uint32_t (*get_fan_control_mode)(struct smu_context *smu);
|
|
|
|
/**
|
|
* @set_fan_control_mode: Set the fan control mode.
|
|
*/
|
|
int (*set_fan_control_mode)(struct smu_context *smu, uint32_t mode);
|
|
|
|
/**
|
|
* @set_fan_speed_percent: Set a static fan speed in percent.
|
|
*/
|
|
int (*set_fan_speed_percent)(struct smu_context *smu, uint32_t speed);
|
|
|
|
/**
|
|
* @set_xgmi_pstate: Set inter-chip global memory interconnect pstate.
|
|
* &pstate: Pstate to set. D0 if Nonzero, D3 otherwise.
|
|
*/
|
|
int (*set_xgmi_pstate)(struct smu_context *smu, uint32_t pstate);
|
|
|
|
/**
|
|
* @gfx_off_control: Enable/disable graphics engine poweroff.
|
|
*/
|
|
int (*gfx_off_control)(struct smu_context *smu, bool enable);
|
|
|
|
|
|
/**
|
|
* @get_gfx_off_status: Get graphics engine poweroff status.
|
|
*
|
|
* Return:
|
|
* 0 - GFXOFF(default).
|
|
* 1 - Transition out of GFX State.
|
|
* 2 - Not in GFXOFF.
|
|
* 3 - Transition into GFXOFF.
|
|
*/
|
|
uint32_t (*get_gfx_off_status)(struct smu_context *smu);
|
|
|
|
/**
|
|
* @register_irq_handler: Register interupt request handlers.
|
|
*/
|
|
int (*register_irq_handler)(struct smu_context *smu);
|
|
|
|
/**
|
|
* @set_azalia_d3_pme: Wake the audio decode engine from d3 sleep.
|
|
*/
|
|
int (*set_azalia_d3_pme)(struct smu_context *smu);
|
|
|
|
/**
|
|
* @get_max_sustainable_clocks_by_dc: Get a copy of the max sustainable
|
|
* clock speeds table.
|
|
*
|
|
* Provides a way for the display component (DC) to get the max
|
|
* sustainable clocks from the SMU.
|
|
*/
|
|
int (*get_max_sustainable_clocks_by_dc)(struct smu_context *smu, struct pp_smu_nv_clock_table *max_clocks);
|
|
|
|
/**
|
|
* @baco_is_support: Check if GPU supports BACO (Bus Active, Chip Off).
|
|
*/
|
|
bool (*baco_is_support)(struct smu_context *smu);
|
|
|
|
/**
|
|
* @baco_get_state: Get the current BACO state.
|
|
*
|
|
* Return: Current BACO state.
|
|
*/
|
|
enum smu_baco_state (*baco_get_state)(struct smu_context *smu);
|
|
|
|
/**
|
|
* @baco_set_state: Enter/exit BACO.
|
|
*/
|
|
int (*baco_set_state)(struct smu_context *smu, enum smu_baco_state state);
|
|
|
|
/**
|
|
* @baco_enter: Enter BACO.
|
|
*/
|
|
int (*baco_enter)(struct smu_context *smu);
|
|
|
|
/**
|
|
* @baco_exit: Exit Baco.
|
|
*/
|
|
int (*baco_exit)(struct smu_context *smu);
|
|
|
|
/**
|
|
* @mode1_reset_is_support: Check if GPU supports mode1 reset.
|
|
*/
|
|
bool (*mode1_reset_is_support)(struct smu_context *smu);
|
|
|
|
/**
|
|
* @mode1_reset: Perform mode1 reset.
|
|
*
|
|
* Complete GPU reset.
|
|
*/
|
|
int (*mode1_reset)(struct smu_context *smu);
|
|
|
|
/**
|
|
* @mode2_reset: Perform mode2 reset.
|
|
*
|
|
* Mode2 reset generally does not reset as many IPs as mode1 reset. The
|
|
* IPs reset varies by asic.
|
|
*/
|
|
int (*mode2_reset)(struct smu_context *smu);
|
|
|
|
/**
|
|
* @get_dpm_ultimate_freq: Get the hard frequency range of a clock
|
|
* domain in MHz.
|
|
*/
|
|
int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max);
|
|
|
|
/**
|
|
* @set_soft_freq_limited_range: Set the soft frequency range of a clock
|
|
* domain in MHz.
|
|
*/
|
|
int (*set_soft_freq_limited_range)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t min, uint32_t max);
|
|
|
|
/**
|
|
* @set_power_source: Notify the SMU of the current power source.
|
|
*/
|
|
int (*set_power_source)(struct smu_context *smu, enum smu_power_src_type power_src);
|
|
|
|
/**
|
|
* @log_thermal_throttling_event: Print a thermal throttling warning to
|
|
* the system's log.
|
|
*/
|
|
void (*log_thermal_throttling_event)(struct smu_context *smu);
|
|
|
|
/**
|
|
* @get_pp_feature_mask: Print a human readable table of enabled
|
|
* features to buffer.
|
|
*/
|
|
size_t (*get_pp_feature_mask)(struct smu_context *smu, char *buf);
|
|
|
|
/**
|
|
* @set_pp_feature_mask: Request the SMU enable/disable features to
|
|
* match those enabled in &new_mask.
|
|
*/
|
|
int (*set_pp_feature_mask)(struct smu_context *smu, uint64_t new_mask);
|
|
|
|
/**
|
|
* @get_gpu_metrics: Get a copy of the GPU metrics table from the SMU.
|
|
*
|
|
* Return: Size of &table
|
|
*/
|
|
ssize_t (*get_gpu_metrics)(struct smu_context *smu, void **table);
|
|
|
|
/**
|
|
* @enable_mgpu_fan_boost: Enable multi-GPU fan boost.
|
|
*/
|
|
int (*enable_mgpu_fan_boost)(struct smu_context *smu);
|
|
|
|
/**
|
|
* @gfx_ulv_control: Enable/disable ultra low voltage.
|
|
*/
|
|
int (*gfx_ulv_control)(struct smu_context *smu, bool enablement);
|
|
|
|
/**
|
|
* @deep_sleep_control: Enable/disable deep sleep.
|
|
*/
|
|
int (*deep_sleep_control)(struct smu_context *smu, bool enablement);
|
|
|
|
/**
|
|
* @get_fan_parameters: Get fan parameters.
|
|
*
|
|
* Get maximum fan speed from the power play table.
|
|
*/
|
|
int (*get_fan_parameters)(struct smu_context *smu);
|
|
|
|
/**
|
|
* @post_init: Helper function for asic specific workarounds.
|
|
*/
|
|
int (*post_init)(struct smu_context *smu);
|
|
|
|
/**
|
|
* @interrupt_work: Work task scheduled from SMU interrupt handler.
|
|
*/
|
|
void (*interrupt_work)(struct smu_context *smu);
|
|
|
|
/**
|
|
* @gpo_control: Enable/disable graphics power optimization if supported.
|
|
*/
|
|
int (*gpo_control)(struct smu_context *smu, bool enablement);
|
|
|
|
/**
|
|
* @gfx_state_change_set: Send the current graphics state to the SMU.
|
|
*/
|
|
int (*gfx_state_change_set)(struct smu_context *smu, uint32_t state);
|
|
|
|
/**
|
|
* @set_fine_grain_gfx_freq_parameters: Set fine grain graphics clock
|
|
* parameters to defaults.
|
|
*/
|
|
int (*set_fine_grain_gfx_freq_parameters)(struct smu_context *smu);
|
|
};
|
|
|
|
typedef enum {
|
|
METRICS_CURR_GFXCLK,
|
|
METRICS_CURR_SOCCLK,
|
|
METRICS_CURR_UCLK,
|
|
METRICS_CURR_VCLK,
|
|
METRICS_CURR_VCLK1,
|
|
METRICS_CURR_DCLK,
|
|
METRICS_CURR_DCLK1,
|
|
METRICS_CURR_FCLK,
|
|
METRICS_CURR_DCEFCLK,
|
|
METRICS_AVERAGE_CPUCLK,
|
|
METRICS_AVERAGE_GFXCLK,
|
|
METRICS_AVERAGE_SOCCLK,
|
|
METRICS_AVERAGE_FCLK,
|
|
METRICS_AVERAGE_UCLK,
|
|
METRICS_AVERAGE_VCLK,
|
|
METRICS_AVERAGE_DCLK,
|
|
METRICS_AVERAGE_GFXACTIVITY,
|
|
METRICS_AVERAGE_MEMACTIVITY,
|
|
METRICS_AVERAGE_VCNACTIVITY,
|
|
METRICS_AVERAGE_SOCKETPOWER,
|
|
METRICS_TEMPERATURE_EDGE,
|
|
METRICS_TEMPERATURE_HOTSPOT,
|
|
METRICS_TEMPERATURE_MEM,
|
|
METRICS_TEMPERATURE_VRGFX,
|
|
METRICS_TEMPERATURE_VRSOC,
|
|
METRICS_TEMPERATURE_VRMEM,
|
|
METRICS_THROTTLER_STATUS,
|
|
METRICS_CURR_FANSPEED,
|
|
METRICS_VOLTAGE_VDDSOC,
|
|
METRICS_VOLTAGE_VDDGFX,
|
|
} MetricsMember_t;
|
|
|
|
enum smu_cmn2asic_mapping_type {
|
|
CMN2ASIC_MAPPING_MSG,
|
|
CMN2ASIC_MAPPING_CLK,
|
|
CMN2ASIC_MAPPING_FEATURE,
|
|
CMN2ASIC_MAPPING_TABLE,
|
|
CMN2ASIC_MAPPING_PWR,
|
|
CMN2ASIC_MAPPING_WORKLOAD,
|
|
};
|
|
|
|
#define MSG_MAP(msg, index, valid_in_vf) \
|
|
[SMU_MSG_##msg] = {1, (index), (valid_in_vf)}
|
|
|
|
#define CLK_MAP(clk, index) \
|
|
[SMU_##clk] = {1, (index)}
|
|
|
|
#define FEA_MAP(fea) \
|
|
[SMU_FEATURE_##fea##_BIT] = {1, FEATURE_##fea##_BIT}
|
|
|
|
#define FEA_MAP_REVERSE(fea) \
|
|
[SMU_FEATURE_DPM_##fea##_BIT] = {1, FEATURE_##fea##_DPM_BIT}
|
|
|
|
#define FEA_MAP_HALF_REVERSE(fea) \
|
|
[SMU_FEATURE_DPM_##fea##CLK_BIT] = {1, FEATURE_##fea##_DPM_BIT}
|
|
|
|
#define TAB_MAP(tab) \
|
|
[SMU_TABLE_##tab] = {1, TABLE_##tab}
|
|
|
|
#define TAB_MAP_VALID(tab) \
|
|
[SMU_TABLE_##tab] = {1, TABLE_##tab}
|
|
|
|
#define TAB_MAP_INVALID(tab) \
|
|
[SMU_TABLE_##tab] = {0, TABLE_##tab}
|
|
|
|
#define PWR_MAP(tab) \
|
|
[SMU_POWER_SOURCE_##tab] = {1, POWER_SOURCE_##tab}
|
|
|
|
#define WORKLOAD_MAP(profile, workload) \
|
|
[profile] = {1, (workload)}
|
|
|
|
#if !defined(SWSMU_CODE_LAYER_L2) && !defined(SWSMU_CODE_LAYER_L3) && !defined(SWSMU_CODE_LAYER_L4)
|
|
int smu_load_microcode(struct smu_context *smu);
|
|
|
|
int smu_check_fw_status(struct smu_context *smu);
|
|
|
|
int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled);
|
|
|
|
int smu_set_fan_speed_rpm(struct smu_context *smu, uint32_t speed);
|
|
|
|
int smu_get_power_limit(struct smu_context *smu,
|
|
uint32_t *limit,
|
|
enum smu_ppt_limit_level limit_level);
|
|
|
|
int smu_set_power_limit(struct smu_context *smu, uint32_t limit);
|
|
int smu_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf);
|
|
|
|
int smu_od_edit_dpm_table(struct smu_context *smu,
|
|
enum PP_OD_DPM_TABLE_COMMAND type,
|
|
long *input, uint32_t size);
|
|
|
|
int smu_read_sensor(struct smu_context *smu,
|
|
enum amd_pp_sensors sensor,
|
|
void *data, uint32_t *size);
|
|
int smu_get_power_profile_mode(struct smu_context *smu, char *buf);
|
|
|
|
int smu_set_power_profile_mode(struct smu_context *smu,
|
|
long *param,
|
|
uint32_t param_size,
|
|
bool lock_needed);
|
|
int smu_get_fan_control_mode(struct smu_context *smu);
|
|
int smu_set_fan_control_mode(struct smu_context *smu, int value);
|
|
int smu_get_fan_speed_percent(struct smu_context *smu, uint32_t *speed);
|
|
int smu_set_fan_speed_percent(struct smu_context *smu, uint32_t speed);
|
|
int smu_get_fan_speed_rpm(struct smu_context *smu, uint32_t *speed);
|
|
|
|
int smu_set_deep_sleep_dcefclk(struct smu_context *smu, int clk);
|
|
|
|
int smu_get_clock_by_type_with_latency(struct smu_context *smu,
|
|
enum smu_clk_type clk_type,
|
|
struct pp_clock_levels_with_latency *clocks);
|
|
|
|
int smu_display_clock_voltage_request(struct smu_context *smu,
|
|
struct pp_display_clock_request *clock_req);
|
|
int smu_display_disable_memory_clock_switch(struct smu_context *smu, bool disable_memory_clock_switch);
|
|
|
|
int smu_set_xgmi_pstate(struct smu_context *smu,
|
|
uint32_t pstate);
|
|
|
|
int smu_set_azalia_d3_pme(struct smu_context *smu);
|
|
|
|
bool smu_baco_is_support(struct smu_context *smu);
|
|
|
|
int smu_baco_get_state(struct smu_context *smu, enum smu_baco_state *state);
|
|
|
|
int smu_baco_enter(struct smu_context *smu);
|
|
int smu_baco_exit(struct smu_context *smu);
|
|
|
|
bool smu_mode1_reset_is_support(struct smu_context *smu);
|
|
int smu_mode1_reset(struct smu_context *smu);
|
|
int smu_mode2_reset(struct smu_context *smu);
|
|
|
|
extern const struct amd_ip_funcs smu_ip_funcs;
|
|
|
|
extern const struct amdgpu_ip_block_version smu_v11_0_ip_block;
|
|
extern const struct amdgpu_ip_block_version smu_v12_0_ip_block;
|
|
|
|
bool is_support_sw_smu(struct amdgpu_device *adev);
|
|
bool is_support_cclk_dpm(struct amdgpu_device *adev);
|
|
int smu_reset(struct smu_context *smu);
|
|
int smu_sys_get_pp_table(struct smu_context *smu, void **table);
|
|
int smu_sys_set_pp_table(struct smu_context *smu, void *buf, size_t size);
|
|
int smu_get_power_num_states(struct smu_context *smu, struct pp_states_info *state_info);
|
|
enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu);
|
|
int smu_write_watermarks_table(struct smu_context *smu);
|
|
int smu_set_watermarks_for_clock_ranges(
|
|
struct smu_context *smu,
|
|
struct pp_smu_wm_range_sets *clock_ranges);
|
|
|
|
/* smu to display interface */
|
|
extern int smu_display_configuration_change(struct smu_context *smu, const
|
|
struct amd_pp_display_configuration
|
|
*display_config);
|
|
extern int smu_dpm_set_power_gate(struct smu_context *smu,uint32_t block_type, bool gate);
|
|
extern int smu_handle_task(struct smu_context *smu,
|
|
enum amd_dpm_forced_level level,
|
|
enum amd_pp_task task_id,
|
|
bool lock_needed);
|
|
int smu_switch_power_profile(struct smu_context *smu,
|
|
enum PP_SMC_POWER_PROFILE type,
|
|
bool en);
|
|
int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
|
|
uint32_t *min, uint32_t *max);
|
|
int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
|
|
uint32_t min, uint32_t max);
|
|
enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu);
|
|
int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level);
|
|
int smu_set_display_count(struct smu_context *smu, uint32_t count);
|
|
int smu_set_ac_dc(struct smu_context *smu);
|
|
size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf);
|
|
int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask);
|
|
int smu_force_clk_levels(struct smu_context *smu,
|
|
enum smu_clk_type clk_type,
|
|
uint32_t mask);
|
|
int smu_set_mp1_state(struct smu_context *smu,
|
|
enum pp_mp1_state mp1_state);
|
|
int smu_set_df_cstate(struct smu_context *smu,
|
|
enum pp_df_cstate state);
|
|
int smu_allow_xgmi_power_down(struct smu_context *smu, bool en);
|
|
|
|
int smu_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
|
|
struct pp_smu_nv_clock_table *max_clocks);
|
|
|
|
int smu_get_uclk_dpm_states(struct smu_context *smu,
|
|
unsigned int *clock_values_in_khz,
|
|
unsigned int *num_states);
|
|
|
|
int smu_get_dpm_clock_table(struct smu_context *smu,
|
|
struct dpm_clocks *clock_table);
|
|
|
|
int smu_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value);
|
|
|
|
ssize_t smu_sys_get_gpu_metrics(struct smu_context *smu, void **table);
|
|
|
|
int smu_enable_mgpu_fan_boost(struct smu_context *smu);
|
|
int smu_gfx_state_change_set(struct smu_context *smu, uint32_t state);
|
|
|
|
#endif
|
|
#endif
|