724ba67515
The arm dts directory has grown to 1559 boards which makes it a bit unwieldy to maintain and use. Past attempts stalled out due to plans to move .dts files out of the kernel tree. Doing that is no longer planned (any time soon at least), so let's go ahead and group .dts files by vendors. This move aligns arm with arm64 .dts file structure. There's no change to dtbs_install as the flat structure is maintained on install. The naming of vendor directories is roughly in this order of preference: - Matching original and current SoC vendor prefix/name (e.g. ti, qcom) - Current vendor prefix/name if still actively sold (SoCs which have been aquired) (e.g. nxp/imx) - Existing platform name for older platforms not sold/maintained by any company (e.g. gemini, nspire) The whole move was scripted with the exception of MAINTAINERS and a few makefile fixups. Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Michal Simek <michal.simek@amd.com> #Xilinx Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Neil Armstrong <neil.armstrong@linaro.org> Acked-by: Paul Barker <paul.barker@sancloud.com> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Wei Xu <xuwei5@hisilicon.com> #hisilicon Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Nick Hawkins <nick.hawkins@hpe.com> Acked-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Acked-by: Peter Rosin <peda@axentia.se> Acked-by: Jesper Nilsson <jesper.nilsson@axis.com> Acked-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> #broadcom Acked-by: Manivannan Sadhasivam <mani@kernel.org> Reviewed-by: Jisheng Zhang <jszhang@kernel.org> Acked-by: Patrice Chotard <patrice.chotard@foss.st.com> Acked-by: Romain Perier <romain.perier@gmail.com> Acked-by: Alexandre TORGUE <alexandre.torgue@st.com> Acked-by: Shawn Guo <shawnguo@kernel.org> Acked-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Acked-by: Enric Balletbo i Serra <eballetbo@gmail.com> Signed-off-by: Rob Herring <robh@kernel.org>
101 lines
2.5 KiB
Text
101 lines
2.5 KiB
Text
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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/*
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* Copyright (C) 2023 DH electronics GmbH
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*
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* DHCOM iMX6ULL variant:
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* DHCM-iMX6ULL-C080-R051-F0409-SPI-E2-CAN2-SD-RTC-ADC-I-01D2
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* DHCOR PCB number: 578-200 or newer
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* DHCOM PCB number: 579-200 or newer
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* PicoITX PCB number: 487-600 or newer
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*/
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/dts-v1/;
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#include "imx6ull-dhcom-som.dtsi"
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#include "imx6ull-dhcom-som-cfg-sdcard.dtsi"
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/ {
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model = "DH electronics i.MX6ULL DHCOM on PicoITX";
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compatible = "dh,imx6ull-dhcom-picoitx", "dh,imx6ull-dhcom-som",
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"dh,imx6ull-dhcor-som", "fsl,imx6ull";
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led {
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compatible = "gpio-leds";
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led-0 {
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color = <LED_COLOR_ID_YELLOW>;
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default-state = "off";
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function = LED_FUNCTION_INDICATOR;
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gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* GPIO I */
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};
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};
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};
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&fec1 {
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phy-handle = <&mdio1_phy0>;
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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mdio1_phy0: ethernet-phy@0 {
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compatible = "ethernet-phy-id0007.c0f0", /* SMSC LAN8710Ai */
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"ethernet-phy-ieee802.3-c22";
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reg = <0>;
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clock-names = "rmii-ref";
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clocks = <&clks IMX6UL_CLK_ENET_REF>;
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interrupt-parent = <&gpio5>;
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interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
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pinctrl-0 = <&pinctrl_fec1_phy &pinctrl_snvs_fec1_phy>;
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pinctrl-names = "default";
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reset-assert-us = <500>;
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reset-deassert-us = <500>;
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reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
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smsc,disable-energy-detect; /* Make plugin detection reliable */
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};
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};
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};
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&fec2 {
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status = "disabled";
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};
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&gpio4 {
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gpio-line-names =
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"", "", "", "",
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"", "", "", "",
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"", "", "", "",
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"", "", "", "",
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"", "PicoITX-HW2", "PicoITX-HW1", "DHCOM-M",
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"PicoITX-HW0", "DHCOM-U", "DHCOM-T", "DHCOM-S",
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"DHCOM-R", "DHCOM-Q", "DHCOM-P", "DHCOM-O",
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"DHCOM-N", "", "", "";
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};
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&gpio5 {
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gpio-line-names =
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"DHCOM-A", "DHCOM-B", "PicoITX-In2", "PicoITX-Out2",
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"PicoITX-In1", "", "", "PicoITX-Out1",
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"DHCOM-G", "DHCOM-H", "", "",
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"", "", "", "",
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"", "", "", "",
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"", "", "", "",
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"", "", "", "",
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"", "", "", "";
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};
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&iomuxc {
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pinctrl_fec1: fec1-grp {
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fsl,pins = <
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MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
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MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
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MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
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MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
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MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
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MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
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MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b010
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MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b010
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MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b010
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MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b010
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>;
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};
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};
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