412d070b31
* Correctly save/restore PMUSERNR_EL0 when host userspace is using
PMU counters directly
* Fix GICv2 emulation on GICv3 after the locking rework
* Don't use smp_processor_id() in kvm_pmu_probe_armpmu(), and
document why
Generic:
* Avoid setting page table entries pointing to a deleted memslot if a
host page table entry is changed concurrently with the deletion.
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Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm
Pull kvm fixes from Paolo Bonzini:
"ARM:
- Correctly save/restore PMUSERNR_EL0 when host userspace is using
PMU counters directly
- Fix GICv2 emulation on GICv3 after the locking rework
- Don't use smp_processor_id() in kvm_pmu_probe_armpmu(), and
document why
Generic:
- Avoid setting page table entries pointing to a deleted memslot if a
host page table entry is changed concurrently with the deletion"
* tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm:
KVM: Avoid illegal stage2 mapping on invalid memory slot
KVM: arm64: Use raw_smp_processor_id() in kvm_pmu_probe_armpmu()
KVM: arm64: Restore GICv2-on-GICv3 functionality
KVM: arm64: PMU: Don't overwrite PMUSERENR with vcpu loaded
KVM: arm64: PMU: Restore the host's PMUSERENR_EL0
252 lines
6.7 KiB
C
252 lines
6.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2012 ARM Ltd.
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*/
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#ifndef __ASM_PMUV3_H
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#define __ASM_PMUV3_H
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#include <asm/cp15.h>
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#include <asm/cputype.h>
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#define PMCCNTR __ACCESS_CP15_64(0, c9)
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#define PMCR __ACCESS_CP15(c9, 0, c12, 0)
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#define PMCNTENSET __ACCESS_CP15(c9, 0, c12, 1)
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#define PMCNTENCLR __ACCESS_CP15(c9, 0, c12, 2)
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#define PMOVSR __ACCESS_CP15(c9, 0, c12, 3)
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#define PMSELR __ACCESS_CP15(c9, 0, c12, 5)
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#define PMCEID0 __ACCESS_CP15(c9, 0, c12, 6)
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#define PMCEID1 __ACCESS_CP15(c9, 0, c12, 7)
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#define PMXEVTYPER __ACCESS_CP15(c9, 0, c13, 1)
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#define PMXEVCNTR __ACCESS_CP15(c9, 0, c13, 2)
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#define PMUSERENR __ACCESS_CP15(c9, 0, c14, 0)
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#define PMINTENSET __ACCESS_CP15(c9, 0, c14, 1)
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#define PMINTENCLR __ACCESS_CP15(c9, 0, c14, 2)
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#define PMMIR __ACCESS_CP15(c9, 0, c14, 6)
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#define PMCCFILTR __ACCESS_CP15(c14, 0, c15, 7)
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#define PMEVCNTR0 __ACCESS_CP15(c14, 0, c8, 0)
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#define PMEVCNTR1 __ACCESS_CP15(c14, 0, c8, 1)
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#define PMEVCNTR2 __ACCESS_CP15(c14, 0, c8, 2)
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#define PMEVCNTR3 __ACCESS_CP15(c14, 0, c8, 3)
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#define PMEVCNTR4 __ACCESS_CP15(c14, 0, c8, 4)
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#define PMEVCNTR5 __ACCESS_CP15(c14, 0, c8, 5)
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#define PMEVCNTR6 __ACCESS_CP15(c14, 0, c8, 6)
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#define PMEVCNTR7 __ACCESS_CP15(c14, 0, c8, 7)
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#define PMEVCNTR8 __ACCESS_CP15(c14, 0, c9, 0)
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#define PMEVCNTR9 __ACCESS_CP15(c14, 0, c9, 1)
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#define PMEVCNTR10 __ACCESS_CP15(c14, 0, c9, 2)
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#define PMEVCNTR11 __ACCESS_CP15(c14, 0, c9, 3)
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#define PMEVCNTR12 __ACCESS_CP15(c14, 0, c9, 4)
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#define PMEVCNTR13 __ACCESS_CP15(c14, 0, c9, 5)
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#define PMEVCNTR14 __ACCESS_CP15(c14, 0, c9, 6)
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#define PMEVCNTR15 __ACCESS_CP15(c14, 0, c9, 7)
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#define PMEVCNTR16 __ACCESS_CP15(c14, 0, c10, 0)
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#define PMEVCNTR17 __ACCESS_CP15(c14, 0, c10, 1)
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#define PMEVCNTR18 __ACCESS_CP15(c14, 0, c10, 2)
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#define PMEVCNTR19 __ACCESS_CP15(c14, 0, c10, 3)
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#define PMEVCNTR20 __ACCESS_CP15(c14, 0, c10, 4)
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#define PMEVCNTR21 __ACCESS_CP15(c14, 0, c10, 5)
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#define PMEVCNTR22 __ACCESS_CP15(c14, 0, c10, 6)
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#define PMEVCNTR23 __ACCESS_CP15(c14, 0, c10, 7)
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#define PMEVCNTR24 __ACCESS_CP15(c14, 0, c11, 0)
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#define PMEVCNTR25 __ACCESS_CP15(c14, 0, c11, 1)
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#define PMEVCNTR26 __ACCESS_CP15(c14, 0, c11, 2)
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#define PMEVCNTR27 __ACCESS_CP15(c14, 0, c11, 3)
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#define PMEVCNTR28 __ACCESS_CP15(c14, 0, c11, 4)
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#define PMEVCNTR29 __ACCESS_CP15(c14, 0, c11, 5)
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#define PMEVCNTR30 __ACCESS_CP15(c14, 0, c11, 6)
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#define PMEVTYPER0 __ACCESS_CP15(c14, 0, c12, 0)
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#define PMEVTYPER1 __ACCESS_CP15(c14, 0, c12, 1)
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#define PMEVTYPER2 __ACCESS_CP15(c14, 0, c12, 2)
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#define PMEVTYPER3 __ACCESS_CP15(c14, 0, c12, 3)
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#define PMEVTYPER4 __ACCESS_CP15(c14, 0, c12, 4)
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#define PMEVTYPER5 __ACCESS_CP15(c14, 0, c12, 5)
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#define PMEVTYPER6 __ACCESS_CP15(c14, 0, c12, 6)
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#define PMEVTYPER7 __ACCESS_CP15(c14, 0, c12, 7)
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#define PMEVTYPER8 __ACCESS_CP15(c14, 0, c13, 0)
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#define PMEVTYPER9 __ACCESS_CP15(c14, 0, c13, 1)
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#define PMEVTYPER10 __ACCESS_CP15(c14, 0, c13, 2)
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#define PMEVTYPER11 __ACCESS_CP15(c14, 0, c13, 3)
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#define PMEVTYPER12 __ACCESS_CP15(c14, 0, c13, 4)
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#define PMEVTYPER13 __ACCESS_CP15(c14, 0, c13, 5)
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#define PMEVTYPER14 __ACCESS_CP15(c14, 0, c13, 6)
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#define PMEVTYPER15 __ACCESS_CP15(c14, 0, c13, 7)
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#define PMEVTYPER16 __ACCESS_CP15(c14, 0, c14, 0)
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#define PMEVTYPER17 __ACCESS_CP15(c14, 0, c14, 1)
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#define PMEVTYPER18 __ACCESS_CP15(c14, 0, c14, 2)
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#define PMEVTYPER19 __ACCESS_CP15(c14, 0, c14, 3)
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#define PMEVTYPER20 __ACCESS_CP15(c14, 0, c14, 4)
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#define PMEVTYPER21 __ACCESS_CP15(c14, 0, c14, 5)
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#define PMEVTYPER22 __ACCESS_CP15(c14, 0, c14, 6)
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#define PMEVTYPER23 __ACCESS_CP15(c14, 0, c14, 7)
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#define PMEVTYPER24 __ACCESS_CP15(c14, 0, c15, 0)
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#define PMEVTYPER25 __ACCESS_CP15(c14, 0, c15, 1)
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#define PMEVTYPER26 __ACCESS_CP15(c14, 0, c15, 2)
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#define PMEVTYPER27 __ACCESS_CP15(c14, 0, c15, 3)
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#define PMEVTYPER28 __ACCESS_CP15(c14, 0, c15, 4)
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#define PMEVTYPER29 __ACCESS_CP15(c14, 0, c15, 5)
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#define PMEVTYPER30 __ACCESS_CP15(c14, 0, c15, 6)
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#define RETURN_READ_PMEVCNTRN(n) \
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return read_sysreg(PMEVCNTR##n)
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static inline unsigned long read_pmevcntrn(int n)
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{
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PMEVN_SWITCH(n, RETURN_READ_PMEVCNTRN);
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return 0;
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}
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#define WRITE_PMEVCNTRN(n) \
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write_sysreg(val, PMEVCNTR##n)
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static inline void write_pmevcntrn(int n, unsigned long val)
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{
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PMEVN_SWITCH(n, WRITE_PMEVCNTRN);
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}
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#define WRITE_PMEVTYPERN(n) \
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write_sysreg(val, PMEVTYPER##n)
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static inline void write_pmevtypern(int n, unsigned long val)
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{
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PMEVN_SWITCH(n, WRITE_PMEVTYPERN);
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}
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static inline unsigned long read_pmmir(void)
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{
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return read_sysreg(PMMIR);
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}
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static inline u32 read_pmuver(void)
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{
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/* PMUVers is not a signed field */
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u32 dfr0 = read_cpuid_ext(CPUID_EXT_DFR0);
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return (dfr0 >> 24) & 0xf;
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}
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static inline void write_pmcr(u32 val)
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{
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write_sysreg(val, PMCR);
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}
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static inline u32 read_pmcr(void)
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{
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return read_sysreg(PMCR);
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}
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static inline void write_pmselr(u32 val)
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{
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write_sysreg(val, PMSELR);
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}
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static inline void write_pmccntr(u64 val)
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{
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write_sysreg(val, PMCCNTR);
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}
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static inline u64 read_pmccntr(void)
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{
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return read_sysreg(PMCCNTR);
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}
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static inline void write_pmxevcntr(u32 val)
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{
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write_sysreg(val, PMXEVCNTR);
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}
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static inline u32 read_pmxevcntr(void)
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{
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return read_sysreg(PMXEVCNTR);
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}
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static inline void write_pmxevtyper(u32 val)
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{
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write_sysreg(val, PMXEVTYPER);
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}
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static inline void write_pmcntenset(u32 val)
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{
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write_sysreg(val, PMCNTENSET);
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}
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static inline void write_pmcntenclr(u32 val)
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{
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write_sysreg(val, PMCNTENCLR);
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}
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static inline void write_pmintenset(u32 val)
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{
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write_sysreg(val, PMINTENSET);
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}
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static inline void write_pmintenclr(u32 val)
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{
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write_sysreg(val, PMINTENCLR);
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}
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static inline void write_pmccfiltr(u32 val)
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{
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write_sysreg(val, PMCCFILTR);
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}
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static inline void write_pmovsclr(u32 val)
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{
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write_sysreg(val, PMOVSR);
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}
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static inline u32 read_pmovsclr(void)
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{
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return read_sysreg(PMOVSR);
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}
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static inline void write_pmuserenr(u32 val)
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{
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write_sysreg(val, PMUSERENR);
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}
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static inline u32 read_pmceid0(void)
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{
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return read_sysreg(PMCEID0);
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}
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static inline u32 read_pmceid1(void)
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{
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return read_sysreg(PMCEID1);
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}
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static inline void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr) {}
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static inline void kvm_clr_pmu_events(u32 clr) {}
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static inline bool kvm_pmu_counter_deferred(struct perf_event_attr *attr)
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{
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return false;
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}
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static inline bool kvm_set_pmuserenr(u64 val)
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{
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return false;
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}
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/* PMU Version in DFR Register */
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#define ARMV8_PMU_DFR_VER_NI 0
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#define ARMV8_PMU_DFR_VER_V3P4 0x5
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#define ARMV8_PMU_DFR_VER_V3P5 0x6
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#define ARMV8_PMU_DFR_VER_IMP_DEF 0xF
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static inline bool pmuv3_implemented(int pmuver)
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{
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return !(pmuver == ARMV8_PMU_DFR_VER_IMP_DEF ||
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pmuver == ARMV8_PMU_DFR_VER_NI);
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}
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static inline bool is_pmuv3p4(int pmuver)
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{
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return pmuver >= ARMV8_PMU_DFR_VER_V3P4;
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}
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static inline bool is_pmuv3p5(int pmuver)
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{
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return pmuver >= ARMV8_PMU_DFR_VER_V3P5;
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}
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#endif
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