2b55915d27
Recent versions of dt-schema warn about a previously undetected
undocumented property:
arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dtb: mmc@20008000: Unevaluated properties are not allowed ('card-detect-delay' was unexpected)
From schema: Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml
There are no GPIOs connected to MSSIO6B4 pin K3 so adding the common
cd-debounce-delay-ms property makes no sense. The Cadence IP has a
register that sets the card detect delay as "DP * tclk". On MPFS, this
clock frequency is not configurable (it must be 200 MHz) & the FPGA
comes out of reset with this register already set.
Fixes: bc47b2217f ("riscv: dts: microchip: add the sundance polarberry")
Fixes: 0fa6107eca ("RISC-V: Initial DTS for Microchip ICICLE board")
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
96 lines
1.4 KiB
Text
96 lines
1.4 KiB
Text
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
|
/* Copyright (c) 2020-2022 Microchip Technology Inc */
|
|
|
|
/dts-v1/;
|
|
|
|
#include "mpfs.dtsi"
|
|
#include "mpfs-polarberry-fabric.dtsi"
|
|
|
|
/* Clock frequency (in Hz) of the rtcclk */
|
|
#define MTIMER_FREQ 1000000
|
|
|
|
/ {
|
|
model = "Sundance PolarBerry";
|
|
compatible = "sundance,polarberry", "microchip,mpfs";
|
|
|
|
aliases {
|
|
ethernet0 = &mac1;
|
|
serial0 = &mmuart0;
|
|
};
|
|
|
|
chosen {
|
|
stdout-path = "serial0:115200n8";
|
|
};
|
|
|
|
cpus {
|
|
timebase-frequency = <MTIMER_FREQ>;
|
|
};
|
|
|
|
ddrc_cache_lo: memory@80000000 {
|
|
device_type = "memory";
|
|
reg = <0x0 0x80000000 0x0 0x2e000000>;
|
|
};
|
|
|
|
ddrc_cache_hi: memory@1000000000 {
|
|
device_type = "memory";
|
|
reg = <0x10 0x00000000 0x0 0xC0000000>;
|
|
};
|
|
};
|
|
|
|
/*
|
|
* phy0 is connected to mac0, but the port itself is on the (optional) carrier
|
|
* board.
|
|
*/
|
|
&mac0 {
|
|
phy-mode = "sgmii";
|
|
phy-handle = <&phy0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
&mac1 {
|
|
phy-mode = "sgmii";
|
|
phy-handle = <&phy1>;
|
|
status = "okay";
|
|
|
|
phy1: ethernet-phy@5 {
|
|
reg = <5>;
|
|
};
|
|
|
|
phy0: ethernet-phy@4 {
|
|
reg = <4>;
|
|
};
|
|
};
|
|
|
|
&mbox {
|
|
status = "okay";
|
|
};
|
|
|
|
&mmc {
|
|
bus-width = <4>;
|
|
disable-wp;
|
|
cap-sd-highspeed;
|
|
cap-mmc-highspeed;
|
|
mmc-ddr-1_8v;
|
|
mmc-hs200-1_8v;
|
|
sd-uhs-sdr12;
|
|
sd-uhs-sdr25;
|
|
sd-uhs-sdr50;
|
|
sd-uhs-sdr104;
|
|
status = "okay";
|
|
};
|
|
|
|
&mmuart0 {
|
|
status = "okay";
|
|
};
|
|
|
|
&refclk {
|
|
clock-frequency = <125000000>;
|
|
};
|
|
|
|
&rtc {
|
|
status = "okay";
|
|
};
|
|
|
|
&syscontroller {
|
|
status = "okay";
|
|
};
|