7dffbdedb9
By the specification the 0xF0000-0xF02FF range is only valid when the DPCD revision is 1.4 or higher. Disable LTTPR support if this isn't so. Trying to detect LTTPRs returned corrupted values for the above DPCD range at least on a Skylake host with an LG 43UD79-B monitor with a DPCD revision 1.2 connected. v2: Add the actual version check. v3: Fix s/DRPX/DPRX/ typo. Fixes:7b2a4ab8b0("drm/i915: Switch to LTTPR transparent mode link training") Cc: <stable@vger.kernel.org> # v5.11 Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210317190149.4032966-1-imre.deak@intel.com (cherry picked from commit264613b406) Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
37 lines
1.2 KiB
C
37 lines
1.2 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2019 Intel Corporation
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*/
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#ifndef __INTEL_DP_LINK_TRAINING_H__
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#define __INTEL_DP_LINK_TRAINING_H__
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#include <drm/drm_dp_helper.h>
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struct intel_crtc_state;
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struct intel_dp;
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int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp);
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void intel_dp_get_adjust_train(struct intel_dp *intel_dp,
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const struct intel_crtc_state *crtc_state,
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enum drm_dp_phy dp_phy,
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const u8 link_status[DP_LINK_STATUS_SIZE]);
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void intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
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const struct intel_crtc_state *crtc_state,
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u8 dp_train_pat);
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void intel_dp_set_signal_levels(struct intel_dp *intel_dp,
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const struct intel_crtc_state *crtc_state,
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enum drm_dp_phy dp_phy);
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void intel_dp_start_link_train(struct intel_dp *intel_dp,
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const struct intel_crtc_state *crtc_state);
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void intel_dp_stop_link_train(struct intel_dp *intel_dp,
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const struct intel_crtc_state *crtc_state);
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/* Get the TPSx symbol type of the value programmed to DP_TRAINING_PATTERN_SET */
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static inline u8 intel_dp_training_pattern_symbol(u8 pattern)
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{
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return pattern & ~DP_LINK_SCRAMBLING_DISABLE;
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}
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#endif /* __INTEL_DP_LINK_TRAINING_H__ */
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