c816723b6b
This was done by the following semantic patch: @@ expression i915; @@ - INTEL_GEN(i915) + GRAPHICS_VER(i915) @@ expression i915; expression E; @@ - INTEL_GEN(i915) >= E + GRAPHICS_VER(i915) >= E @@ expression dev_priv; expression E; @@ - !IS_GEN(dev_priv, E) + GRAPHICS_VER(dev_priv) != E @@ expression dev_priv; expression E; @@ - IS_GEN(dev_priv, E) + GRAPHICS_VER(dev_priv) == E @@ expression dev_priv; expression from, until; @@ - IS_GEN_RANGE(dev_priv, from, until) + IS_GRAPHICS_VER(dev_priv, from, until) @def@ expression E; identifier id =~ "^gen$"; @@ - id = GRAPHICS_VER(E) + ver = GRAPHICS_VER(E) @@ identifier def.id; @@ - id + ver It also takes care of renaming the variable we assign to GRAPHICS_VER() so to use "ver" rather than "gen". Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210605155356.4183026-2-lucas.demarchi@intel.com
108 lines
2.4 KiB
C
108 lines
2.4 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2019 Intel Corporation
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*/
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#include "i915_drv.h"
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#include "i915_reg.h"
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#include "intel_gt.h"
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#include "intel_gt_irq.h"
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#include "intel_gt_pm_irq.h"
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static void write_pm_imr(struct intel_gt *gt)
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{
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struct drm_i915_private *i915 = gt->i915;
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struct intel_uncore *uncore = gt->uncore;
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u32 mask = gt->pm_imr;
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i915_reg_t reg;
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if (GRAPHICS_VER(i915) >= 11) {
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reg = GEN11_GPM_WGBOXPERF_INTR_MASK;
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mask <<= 16; /* pm is in upper half */
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} else if (GRAPHICS_VER(i915) >= 8) {
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reg = GEN8_GT_IMR(2);
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} else {
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reg = GEN6_PMIMR;
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}
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intel_uncore_write(uncore, reg, mask);
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}
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static void gen6_gt_pm_update_irq(struct intel_gt *gt,
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u32 interrupt_mask,
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u32 enabled_irq_mask)
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{
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u32 new_val;
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WARN_ON(enabled_irq_mask & ~interrupt_mask);
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lockdep_assert_held(>->irq_lock);
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new_val = gt->pm_imr;
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new_val &= ~interrupt_mask;
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new_val |= ~enabled_irq_mask & interrupt_mask;
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if (new_val != gt->pm_imr) {
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gt->pm_imr = new_val;
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write_pm_imr(gt);
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}
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}
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void gen6_gt_pm_unmask_irq(struct intel_gt *gt, u32 mask)
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{
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gen6_gt_pm_update_irq(gt, mask, mask);
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}
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void gen6_gt_pm_mask_irq(struct intel_gt *gt, u32 mask)
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{
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gen6_gt_pm_update_irq(gt, mask, 0);
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}
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void gen6_gt_pm_reset_iir(struct intel_gt *gt, u32 reset_mask)
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{
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struct intel_uncore *uncore = gt->uncore;
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i915_reg_t reg = GRAPHICS_VER(gt->i915) >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
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lockdep_assert_held(>->irq_lock);
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intel_uncore_write(uncore, reg, reset_mask);
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intel_uncore_write(uncore, reg, reset_mask);
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intel_uncore_posting_read(uncore, reg);
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}
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static void write_pm_ier(struct intel_gt *gt)
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{
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struct drm_i915_private *i915 = gt->i915;
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struct intel_uncore *uncore = gt->uncore;
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u32 mask = gt->pm_ier;
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i915_reg_t reg;
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if (GRAPHICS_VER(i915) >= 11) {
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reg = GEN11_GPM_WGBOXPERF_INTR_ENABLE;
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mask <<= 16; /* pm is in upper half */
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} else if (GRAPHICS_VER(i915) >= 8) {
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reg = GEN8_GT_IER(2);
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} else {
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reg = GEN6_PMIER;
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}
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intel_uncore_write(uncore, reg, mask);
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}
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void gen6_gt_pm_enable_irq(struct intel_gt *gt, u32 enable_mask)
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{
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lockdep_assert_held(>->irq_lock);
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gt->pm_ier |= enable_mask;
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write_pm_ier(gt);
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gen6_gt_pm_unmask_irq(gt, enable_mask);
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}
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void gen6_gt_pm_disable_irq(struct intel_gt *gt, u32 disable_mask)
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{
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lockdep_assert_held(>->irq_lock);
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gt->pm_ier &= ~disable_mask;
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gen6_gt_pm_mask_irq(gt, disable_mask);
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write_pm_ier(gt);
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}
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