Robin Singh 19cc1f3829 drm/amd/display: fixed divide by zero kernel crash during dsc enablement ... [why] During dsc enable, a divide by zero condition triggered the kernel crash. [how] An IGT test, which enable the DSC, was crashing at the time of restore the default dsc status, becaue of h_totals value becoming 0. So add a check before divide condition. If h_total is zero, gracefully ignore and set the default value. kernel panic log: [ 128.758827] divide error: 0000 [#1] PREEMPT SMP NOPTI [ 128.762714] CPU: 5 PID: 4562 Comm: amd_dp_dsc Tainted: G W 5.4.19-android-x86_64 #1 [ 128.769728] Hardware name: ADVANCED MICRO DEVICES, INC. Mauna/Mauna, BIOS WMN0B13N Nov 11 2020 [ 128.777695] RIP: 0010:hubp2_vready_at_or_After_vsync+0x37/0x7a [amdgpu] [ 128.785707] Code: 80 02 00 00 48 89 f3 48 8b 7f 08 b ...... [ 128.805696] RSP: 0018:ffffad8f82d43628 EFLAGS: 00010246 ...... [ 128.857707] CR2: 00007106d8465000 CR3: 0000000426530000 CR4: 0000000000140ee0 [ 128.865695] Call Trace: [ 128.869712] hubp3_setup+0x1f/0x7f [amdgpu] [ 128.873705] dcn20_update_dchubp_dpp+0xc8/0x54a [amdgpu] [ 128.877706] dcn20_program_front_end_for_ctx+0x31d/0x463 [amdgpu] [ 128.885706] dc_commit_state+0x3d2/0x658 [amdgpu] [ 128.889707] amdgpu_dm_atomic_commit_tail+0x4b3/0x1e7c [amdgpu] [ 128.897699] ? dm_read_reg_func+0x41/0xb5 [amdgpu] [ 128.901707] ? dm_read_reg_func+0x41/0xb5 [amdgpu] [ 128.905706] ? __is_insn_slot_addr+0x43/0x48 [ 128.909706] ? fill_plane_buffer_attributes+0x29e/0x3dc [amdgpu] [ 128.917705] ? dm_plane_helper_prepare_fb+0x255/0x284 [amdgpu] [ 128.921700] ? usleep_range+0x7c/0x7c [ 128.925705] ? preempt_count_sub+0xf/0x18 [ 128.929706] ? _raw_spin_unlock_irq+0x13/0x24 [ 128.933732] ? __wait_for_common+0x11e/0x18f [ 128.937705] ? _raw_spin_unlock_irq+0x13/0x24 [ 128.941706] ? __wait_for_common+0x11e/0x18f [ 128.945705] commit_tail+0x8b/0xd2 [drm_kms_helper] [ 128.949707] drm_atomic_helper_commit+0xd8/0xf5 [drm_kms_helper] [ 128.957706] amdgpu_dm_atomic_commit+0x337/0x360 [amdgpu] [ 128.961705] ? drm_atomic_check_only+0x543/0x68d [drm] [ 128.969705] ? drm_atomic_set_property+0x760/0x7af [drm] [ 128.973704] ? drm_mode_atomic_ioctl+0x6f3/0x85a [drm] [ 128.977705] drm_mode_atomic_ioctl+0x6f3/0x85a [drm] [ 128.985705] ? drm_atomic_set_property+0x7af/0x7af [drm] [ 128.989706] drm_ioctl_kernel+0x82/0xda [drm] [ 128.993706] drm_ioctl+0x225/0x319 [drm] [ 128.997707] ? drm_atomic_set_property+0x7af/0x7af [drm] [ 129.001706] ? preempt_count_sub+0xf/0x18 [ 129.005713] amdgpu_drm_ioctl+0x4b/0x76 [amdgpu] [ 129.009705] vfs_ioctl+0x1d/0x2a [ 129.013705] do_vfs_ioctl+0x419/0x43d [ 129.017707] ksys_ioctl+0x52/0x71 [ 129.021707] __x64_sys_ioctl+0x16/0x19 [ 129.025706] do_syscall_64+0x78/0x85 [ 129.029705] entry_SYSCALL_64_after_hwframe+0x44/0xa9 Signed-off-by: Robin Singh <robin.singh@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Robin Singh <Robin.Singh@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2021-04-20 21:36:41 -04:00
..
dcn20_dccg.c	drm/amd/display: use GFP_ATOMIC in dcn20_resource_construct	2021-04-09 16:38:22 -04:00
dcn20_dccg.h	drm/amdgpu: fold CONFIG_DRM_AMD_DC_DCN3* into CONFIG_DRM_AMD_DC_DCN (v3)	2020-11-04 17:11:37 -05:00
dcn20_dpp.c	drm/amd/display: correct alpha_en programming for new pixel format	2020-07-01 01:59:19 -04:00
dcn20_dpp.h	drm/amd/display: Add DSCL memory low power support	2020-12-01 16:03:40 -05:00
dcn20_dpp_cm.c	drm/amd/display: Indirect reg read macro with shift and mask	2020-01-16 14:13:53 -05:00
dcn20_dsc.c	drm/amd/display: Rename bytes_pp to the correct bits_pp	2020-07-27 16:23:21 -04:00
dcn20_dsc.h	drm/amd/display: Add DSC_DBG_EN shift/mask for dcn3	2020-08-17 14:09:27 -04:00
dcn20_dwb.c	drm/amd/display: [backport] dwb dm + efc support	2019-06-22 09:34:11 -05:00
dcn20_dwb.h	drm/amd/display: Add DCN2 DWB	2019-06-21 18:59:35 -05:00
dcn20_dwb_scl.c	drm/amd/display: Remove set but not used variables 'h_ratio_chroma', 'v_ratio_chroma'	2019-10-07 15:10:43 -05:00
dcn20_hubbub.c	drm/amdgpu: fold CONFIG_DRM_AMD_DC_DCN3* into CONFIG_DRM_AMD_DC_DCN (v3)	2020-11-04 17:11:37 -05:00
dcn20_hubbub.h	drm/amd/display: correct rn NUM_VMID	2020-05-21 12:48:43 -04:00
dcn20_hubp.c	drm/amd/display: fixed divide by zero kernel crash during dsc enablement	2021-04-20 21:36:41 -04:00
dcn20_hubp.h	drm/amdgpu: fold CONFIG_DRM_AMD_DC_DCN3* into CONFIG_DRM_AMD_DC_DCN (v3)	2020-11-04 17:11:37 -05:00
dcn20_hwseq.c	drm/amd/display: Remove MPC gamut remap logic for DCN30	2021-03-23 23:32:42 -04:00
dcn20_hwseq.h	drm/amd/display: Blank HUBP during pixel data blank for DCN30 v2	2020-11-02 15:31:30 -05:00
dcn20_init.c	drm/amd/display: Add function and debugfs to dump DCC_EN bit	2021-04-09 16:52:03 -04:00
dcn20_init.h	drm/amd/display: cleanup of function pointer tables	2019-11-19 10:12:53 -05:00
dcn20_link_encoder.c	drm/amdgpu/display: restore AUX_DPHY_TX_CONTROL for DCN2.x	2021-04-09 16:38:31 -04:00
dcn20_link_encoder.h	drm/amdgpu: fold CONFIG_DRM_AMD_DC_DCN3* into CONFIG_DRM_AMD_DC_DCN (v3)	2020-11-04 17:11:37 -05:00
dcn20_mmhubbub.c	drm/amd/display: Add DCN2 MMHUBBUB	2019-06-21 18:59:34 -05:00
dcn20_mmhubbub.h	drm/amd/display: Update register defines	2020-02-11 11:50:18 -05:00
dcn20_mpc.c	drm/amd/display: add getter routine to retrieve mpcc mux	2020-12-23 15:02:55 -05:00
dcn20_mpc.h	drm/amd/display: Use cursor locking to prevent flip delays	2020-04-28 16:19:56 -04:00
dcn20_opp.c	drm/amd/display: Raise DPG height during timing synchronization	2020-10-26 13:29:21 -04:00
dcn20_opp.h	drm/amd/display: Raise DPG height during timing synchronization	2020-10-26 13:29:21 -04:00
dcn20_optc.c	drm/amd/display: Move vupdate keepout programming from DCN20 to DCN10	2021-04-09 16:51:44 -04:00
dcn20_optc.h	drm/amd/display: Move vupdate keepout programming from DCN20 to DCN10	2021-04-09 16:51:44 -04:00
dcn20_resource.c	drm/amd/display: Fix DML validation of simple vs native 422 modes	2021-04-15 16:31:24 -04:00
dcn20_resource.h	drm/amd/display: Prevent freesync power optimization during validation	2020-11-10 14:24:48 -05:00
dcn20_stream_encoder.c	drm/amd/display: Rename set_mst_bandwidth to align with DP spec	2020-09-15 17:52:41 -04:00
dcn20_stream_encoder.h	drm/amd/display: Add missing DP_SEC register definitions and masks	2020-12-15 11:33:33 -05:00
dcn20_vmid.c	drm/amd/display: Poll for GPUVM context ready (v2)	2019-07-18 14:18:09 -05:00
dcn20_vmid.h	drm/amd/display: Update register defines	2020-02-11 11:50:18 -05:00
Makefile	drm/amdgpu/display: drop DCN support for aarch64	2021-01-05 11:35:53 -05:00