729a866af3
Added processor thermal device mail box interface for workload hints setting. These hints will give indication to hardware to better manage power and thermals. The supported hints are: idle semi_active burusty sustained battery_life For example when the system is on battery, the hardware can be less aggressive in power ramp up. This will create an attribute group at /sys/bus/pci/devices/0000:00:04.0/workload_request This folder contains two attributes: workload_available_types : (RO): This shows available workload types workload_type: (RW) : Allows to set and get current workload type setting Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/20201126171829.945969-4-srinivas.pandruvada@linux.intel.com
82 lines
2.2 KiB
C
82 lines
2.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* processor_thermal_device.h
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* Copyright (c) 2020, Intel Corporation.
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*/
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#ifndef __PROCESSOR_THERMAL_DEVICE_H__
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#define __PROCESSOR_THERMAL_DEVICE_H__
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#include <linux/intel_rapl.h>
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#define PCI_DEVICE_ID_INTEL_ADL_THERMAL 0x461d
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#define PCI_DEVICE_ID_INTEL_BDW_THERMAL 0x1603
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#define PCI_DEVICE_ID_INTEL_BSW_THERMAL 0x22DC
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#define PCI_DEVICE_ID_INTEL_BXT0_THERMAL 0x0A8C
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#define PCI_DEVICE_ID_INTEL_BXT1_THERMAL 0x1A8C
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#define PCI_DEVICE_ID_INTEL_BXTX_THERMAL 0x4A8C
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#define PCI_DEVICE_ID_INTEL_BXTP_THERMAL 0x5A8C
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#define PCI_DEVICE_ID_INTEL_CNL_THERMAL 0x5a03
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#define PCI_DEVICE_ID_INTEL_CFL_THERMAL 0x3E83
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#define PCI_DEVICE_ID_INTEL_GLK_THERMAL 0x318C
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#define PCI_DEVICE_ID_INTEL_HSB_THERMAL 0x0A03
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#define PCI_DEVICE_ID_INTEL_ICL_THERMAL 0x8a03
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#define PCI_DEVICE_ID_INTEL_JSL_THERMAL 0x4E03
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#define PCI_DEVICE_ID_INTEL_SKL_THERMAL 0x1903
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#define PCI_DEVICE_ID_INTEL_TGL_THERMAL 0x9A03
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struct power_config {
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u32 index;
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u32 min_uw;
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u32 max_uw;
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u32 tmin_us;
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u32 tmax_us;
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u32 step_uw;
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};
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struct proc_thermal_device {
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struct device *dev;
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struct acpi_device *adev;
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struct power_config power_limits[2];
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struct int34x_thermal_zone *int340x_zone;
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struct intel_soc_dts_sensors *soc_dts;
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u32 mmio_feature_mask;
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void __iomem *mmio_base;
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};
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struct rapl_mmio_regs {
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u64 reg_unit;
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u64 regs[RAPL_DOMAIN_MAX][RAPL_DOMAIN_REG_MAX];
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int limits[RAPL_DOMAIN_MAX];
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};
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#define PROC_THERMAL_FEATURE_NONE 0x00
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#define PROC_THERMAL_FEATURE_RAPL 0x01
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#define PROC_THERMAL_FEATURE_FIVR 0x02
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#define PROC_THERMAL_FEATURE_DVFS 0x04
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#define PROC_THERMAL_FEATURE_MBOX 0x08
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#if IS_ENABLED(CONFIG_PROC_THERMAL_MMIO_RAPL)
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int proc_thermal_rapl_add(struct pci_dev *pdev, struct proc_thermal_device *proc_priv);
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void proc_thermal_rapl_remove(void);
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#else
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static int __maybe_unused proc_thermal_rapl_add(struct pci_dev *pdev,
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struct proc_thermal_device *proc_priv)
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{
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return 0;
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}
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static void __maybe_unused proc_thermal_rapl_remove(void)
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{
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}
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#endif
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int proc_thermal_rfim_add(struct pci_dev *pdev, struct proc_thermal_device *proc_priv);
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void proc_thermal_rfim_remove(struct pci_dev *pdev);
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int proc_thermal_mbox_add(struct pci_dev *pdev, struct proc_thermal_device *proc_priv);
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void proc_thermal_mbox_remove(struct pci_dev *pdev);
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#endif
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