8ae5b1d78d
[Why] The new aux implementation was not up to spec. This caused us to fail DP compliance as well as introduced serious delays during system resume. [How] Make dce_aux_transfer_raw return the operation result Make dce_aux_transfer_with_retries delay with udelay instead of msleep, and only on invalid reply. Also fail on the second invalid reply, third timeout, or first of any other error Convert return values to drm error codes in amdgpu_dm As the two aux transfer functions are now noticeably different, change the names to better reflect their functionality and document. There was one last call to dc_link_aux_transfer that should have retries, fix that Signed-off-by: David Francis <David.Francis@amd.com> Signed-off-by: Thomas Lim <Thomas.Lim@amd.com> Reviewed-by: David Francis <David.Francis@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Acked-by: Eric Yang <eric.yang2@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
132 lines
4 KiB
C
132 lines
4 KiB
C
/*
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* Copyright 2012-15 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef __DAL_AUX_ENGINE_DCE110_H__
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#define __DAL_AUX_ENGINE_DCE110_H__
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#include "i2caux_interface.h"
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#include "inc/hw/aux_engine.h"
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#define AUX_COMMON_REG_LIST(id)\
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SRI(AUX_CONTROL, DP_AUX, id), \
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SRI(AUX_ARB_CONTROL, DP_AUX, id), \
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SRI(AUX_SW_DATA, DP_AUX, id), \
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SRI(AUX_SW_CONTROL, DP_AUX, id), \
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SRI(AUX_INTERRUPT_CONTROL, DP_AUX, id), \
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SRI(AUX_SW_STATUS, DP_AUX, id), \
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SR(AUXN_IMPCAL), \
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SR(AUXP_IMPCAL)
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struct dce110_aux_registers {
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uint32_t AUX_CONTROL;
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uint32_t AUX_ARB_CONTROL;
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uint32_t AUX_SW_DATA;
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uint32_t AUX_SW_CONTROL;
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uint32_t AUX_INTERRUPT_CONTROL;
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uint32_t AUX_SW_STATUS;
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uint32_t AUXN_IMPCAL;
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uint32_t AUXP_IMPCAL;
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uint32_t AUX_RESET_MASK;
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};
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enum { /* This is the timeout as defined in DP 1.2a,
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* 2.3.4 "Detailed uPacket TX AUX CH State Description".
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*/
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AUX_TIMEOUT_PERIOD = 400,
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/* Ideally, the SW timeout should be just above 550usec
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* which is programmed in HW.
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* But the SW timeout of 600usec is not reliable,
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* because on some systems, delay_in_microseconds()
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* returns faster than it should.
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* EPR #379763: by trial-and-error on different systems,
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* 700usec is the minimum reliable SW timeout for polling
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* the AUX_SW_STATUS.AUX_SW_DONE bit.
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* This timeout expires *only* when there is
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* AUX Error or AUX Timeout conditions - not during normal operation.
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* During normal operation, AUX_SW_STATUS.AUX_SW_DONE bit is set
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* at most within ~240usec. That means,
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* increasing this timeout will not affect normal operation,
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* and we'll timeout after
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* SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD = 1600usec.
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* This timeout is especially important for
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* resume from S3 and CTS.
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*/
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SW_AUX_TIMEOUT_PERIOD_MULTIPLIER = 4
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};
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struct dce_aux {
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uint32_t inst;
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struct ddc *ddc;
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struct dc_context *ctx;
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/* following values are expressed in milliseconds */
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uint32_t delay;
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uint32_t max_defer_write_retry;
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bool acquire_reset;
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};
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struct aux_engine_dce110 {
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struct dce_aux base;
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const struct dce110_aux_registers *regs;
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struct {
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uint32_t aux_control;
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uint32_t aux_arb_control;
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uint32_t aux_sw_data;
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uint32_t aux_sw_control;
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uint32_t aux_interrupt_control;
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uint32_t aux_sw_status;
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} addr;
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uint32_t timeout_period;
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};
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struct aux_engine_dce110_init_data {
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uint32_t engine_id;
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uint32_t timeout_period;
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struct dc_context *ctx;
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const struct dce110_aux_registers *regs;
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};
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struct dce_aux *dce110_aux_engine_construct(
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struct aux_engine_dce110 *aux_engine110,
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struct dc_context *ctx,
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uint32_t inst,
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uint32_t timeout_period,
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const struct dce110_aux_registers *regs);
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void dce110_engine_destroy(struct dce_aux **engine);
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bool dce110_aux_engine_acquire(
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struct dce_aux *aux_engine,
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struct ddc *ddc);
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int dce_aux_transfer_raw(struct ddc_service *ddc,
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struct aux_payload *cmd,
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enum aux_channel_operation_result *operation_result);
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bool dce_aux_transfer_with_retries(struct ddc_service *ddc,
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struct aux_payload *cmd);
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#endif
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