d54ee94603
Initializing ABM and DMCU modules for dce 80/81/83/100 as in DCE110 Adding constructors and destructors for each module. Adding register list for DMCU in dce80 as some registers are missing in dce80 from the basic list. DMCU is never used, so it would not have any functional impact. Signed-off-by: Mikita Lipski <mikita.lipski@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
266 lines
8.5 KiB
C
266 lines
8.5 KiB
C
/*
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* Copyright 2012-16 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef _DCE_DMCU_H_
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#define _DCE_DMCU_H_
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#include "dmcu.h"
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#define DMCU_COMMON_REG_LIST_DCE_BASE() \
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SR(DMCU_CTRL), \
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SR(DMCU_STATUS), \
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SR(DMCU_RAM_ACCESS_CTRL), \
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SR(DMCU_IRAM_WR_CTRL), \
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SR(DMCU_IRAM_WR_DATA), \
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SR(MASTER_COMM_DATA_REG1), \
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SR(MASTER_COMM_DATA_REG2), \
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SR(MASTER_COMM_DATA_REG3), \
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SR(MASTER_COMM_CMD_REG), \
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SR(MASTER_COMM_CNTL_REG), \
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SR(DMCU_IRAM_RD_CTRL), \
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SR(DMCU_IRAM_RD_DATA), \
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SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \
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SR(SMU_INTERRUPT_CONTROL), \
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SR(DC_DMCU_SCRATCH)
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#define DMCU_DCE80_REG_LIST() \
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SR(DMCU_CTRL), \
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SR(DMCU_STATUS), \
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SR(DMCU_RAM_ACCESS_CTRL), \
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SR(DMCU_IRAM_WR_CTRL), \
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SR(DMCU_IRAM_WR_DATA), \
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SR(MASTER_COMM_DATA_REG1), \
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SR(MASTER_COMM_DATA_REG2), \
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SR(MASTER_COMM_DATA_REG3), \
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SR(MASTER_COMM_CMD_REG), \
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SR(MASTER_COMM_CNTL_REG), \
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SR(DMCU_IRAM_RD_CTRL), \
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SR(DMCU_IRAM_RD_DATA), \
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SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \
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SR(SMU_INTERRUPT_CONTROL), \
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SR(DC_DMCU_SCRATCH)
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#define DMCU_DCE110_COMMON_REG_LIST() \
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DMCU_COMMON_REG_LIST_DCE_BASE(), \
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SR(DCI_MEM_PWR_STATUS)
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#define DMCU_DCN10_REG_LIST()\
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DMCU_COMMON_REG_LIST_DCE_BASE(), \
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SR(DMU_MEM_PWR_CNTL)
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#define DMCU_SF(reg_name, field_name, post_fix)\
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.field_name = reg_name ## __ ## field_name ## post_fix
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#define DMCU_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \
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DMCU_SF(DMCU_CTRL, \
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DMCU_ENABLE, mask_sh), \
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DMCU_SF(DMCU_STATUS, \
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UC_IN_STOP_MODE, mask_sh), \
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DMCU_SF(DMCU_STATUS, \
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UC_IN_RESET, mask_sh), \
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DMCU_SF(DMCU_RAM_ACCESS_CTRL, \
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IRAM_HOST_ACCESS_EN, mask_sh), \
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DMCU_SF(DMCU_RAM_ACCESS_CTRL, \
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IRAM_WR_ADDR_AUTO_INC, mask_sh), \
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DMCU_SF(DMCU_RAM_ACCESS_CTRL, \
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IRAM_RD_ADDR_AUTO_INC, mask_sh), \
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DMCU_SF(MASTER_COMM_CMD_REG, \
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MASTER_COMM_CMD_REG_BYTE0, mask_sh), \
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DMCU_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh), \
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DMCU_SF(DMCU_INTERRUPT_TO_UC_EN_MASK, \
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STATIC_SCREEN1_INT_TO_UC_EN, mask_sh), \
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DMCU_SF(DMCU_INTERRUPT_TO_UC_EN_MASK, \
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STATIC_SCREEN2_INT_TO_UC_EN, mask_sh), \
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DMCU_SF(DMCU_INTERRUPT_TO_UC_EN_MASK, \
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STATIC_SCREEN3_INT_TO_UC_EN, mask_sh), \
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DMCU_SF(DMCU_INTERRUPT_TO_UC_EN_MASK, \
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STATIC_SCREEN4_INT_TO_UC_EN, mask_sh), \
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DMCU_SF(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, mask_sh)
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#define DMCU_MASK_SH_LIST_DCE80(mask_sh) \
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DMCU_SF(DMCU_CTRL, \
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DMCU_ENABLE, mask_sh), \
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DMCU_SF(DMCU_STATUS, \
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UC_IN_STOP_MODE, mask_sh), \
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DMCU_SF(DMCU_STATUS, \
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UC_IN_RESET, mask_sh), \
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DMCU_SF(DMCU_RAM_ACCESS_CTRL, \
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IRAM_HOST_ACCESS_EN, mask_sh), \
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DMCU_SF(DMCU_RAM_ACCESS_CTRL, \
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IRAM_WR_ADDR_AUTO_INC, mask_sh), \
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DMCU_SF(DMCU_RAM_ACCESS_CTRL, \
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IRAM_RD_ADDR_AUTO_INC, mask_sh), \
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DMCU_SF(MASTER_COMM_CMD_REG, \
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MASTER_COMM_CMD_REG_BYTE0, mask_sh), \
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DMCU_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh), \
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DMCU_SF(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, mask_sh)
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#define DMCU_MASK_SH_LIST_DCE110(mask_sh) \
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DMCU_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \
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DMCU_SF(DCI_MEM_PWR_STATUS, \
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DMCU_IRAM_MEM_PWR_STATE, mask_sh)
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#define DMCU_MASK_SH_LIST_DCN10(mask_sh) \
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DMCU_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \
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DMCU_SF(DMU_MEM_PWR_CNTL, \
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DMCU_IRAM_MEM_PWR_STATE, mask_sh)
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#define DMCU_REG_FIELD_LIST(type) \
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type DMCU_IRAM_MEM_PWR_STATE; \
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type IRAM_HOST_ACCESS_EN; \
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type IRAM_WR_ADDR_AUTO_INC; \
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type IRAM_RD_ADDR_AUTO_INC; \
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type DMCU_ENABLE; \
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type UC_IN_STOP_MODE; \
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type UC_IN_RESET; \
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type MASTER_COMM_CMD_REG_BYTE0; \
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type MASTER_COMM_INTERRUPT; \
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type DPHY_RX_FAST_TRAINING_CAPABLE; \
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type DPHY_LOAD_BS_COUNT; \
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type STATIC_SCREEN1_INT_TO_UC_EN; \
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type STATIC_SCREEN2_INT_TO_UC_EN; \
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type STATIC_SCREEN3_INT_TO_UC_EN; \
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type STATIC_SCREEN4_INT_TO_UC_EN; \
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type DP_SEC_GSP0_LINE_NUM; \
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type DP_SEC_GSP0_PRIORITY; \
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type DC_SMU_INT_ENABLE
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struct dce_dmcu_shift {
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DMCU_REG_FIELD_LIST(uint8_t);
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};
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struct dce_dmcu_mask {
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DMCU_REG_FIELD_LIST(uint32_t);
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};
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struct dce_dmcu_registers {
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uint32_t DMCU_CTRL;
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uint32_t DMCU_STATUS;
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uint32_t DMCU_RAM_ACCESS_CTRL;
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uint32_t DCI_MEM_PWR_STATUS;
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uint32_t DMU_MEM_PWR_CNTL;
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uint32_t DMCU_IRAM_WR_CTRL;
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uint32_t DMCU_IRAM_WR_DATA;
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uint32_t MASTER_COMM_DATA_REG1;
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uint32_t MASTER_COMM_DATA_REG2;
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uint32_t MASTER_COMM_DATA_REG3;
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uint32_t MASTER_COMM_CMD_REG;
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uint32_t MASTER_COMM_CNTL_REG;
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uint32_t DMCU_IRAM_RD_CTRL;
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uint32_t DMCU_IRAM_RD_DATA;
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uint32_t DMCU_INTERRUPT_TO_UC_EN_MASK;
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uint32_t SMU_INTERRUPT_CONTROL;
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uint32_t DC_DMCU_SCRATCH;
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};
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struct dce_dmcu {
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struct dmcu base;
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const struct dce_dmcu_registers *regs;
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const struct dce_dmcu_shift *dmcu_shift;
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const struct dce_dmcu_mask *dmcu_mask;
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};
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/*******************************************************************
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* MASTER_COMM_DATA_REG1 Bit position Data
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* 7:0 hyst_frames[7:0]
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* 14:8 hyst_lines[6:0]
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* 15 RFB_UPDATE_AUTO_EN
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* 18:16 phy_num[2:0]
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* 21:19 dcp_sel[2:0]
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* 22 phy_type
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* 23 frame_cap_ind
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* 26:24 aux_chan[2:0]
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* 30:27 aux_repeat[3:0]
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* 31:31 reserved[31:31]
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******************************************************************/
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union dce_dmcu_psr_config_data_reg1 {
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struct {
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unsigned int timehyst_frames:8; /*[7:0]*/
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unsigned int hyst_lines:7; /*[14:8]*/
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unsigned int rfb_update_auto_en:1; /*[15:15]*/
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unsigned int dp_port_num:3; /*[18:16]*/
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unsigned int dcp_sel:3; /*[21:19]*/
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unsigned int phy_type:1; /*[22:22]*/
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unsigned int frame_cap_ind:1; /*[23:23]*/
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unsigned int aux_chan:3; /*[26:24]*/
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unsigned int aux_repeat:4; /*[30:27]*/
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unsigned int reserved:1; /*[31:31]*/
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} bits;
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unsigned int u32All;
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};
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/*******************************************************************
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* MASTER_COMM_DATA_REG2
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*******************************************************************/
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union dce_dmcu_psr_config_data_reg2 {
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struct {
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unsigned int dig_fe:3; /*[2:0]*/
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unsigned int dig_be:3; /*[5:3]*/
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unsigned int skip_wait_for_pll_lock:1; /*[6:6]*/
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unsigned int reserved:9; /*[15:7]*/
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unsigned int frame_delay:8; /*[23:16]*/
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unsigned int smu_phy_id:4; /*[27:24]*/
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unsigned int num_of_controllers:4; /*[31:28]*/
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} bits;
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unsigned int u32All;
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};
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/*******************************************************************
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* MASTER_COMM_DATA_REG3
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*******************************************************************/
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union dce_dmcu_psr_config_data_reg3 {
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struct {
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unsigned int psr_level:16; /*[15:0]*/
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unsigned int link_rate:4; /*[19:16]*/
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unsigned int reserved:12; /*[31:20]*/
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} bits;
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unsigned int u32All;
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};
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union dce_dmcu_psr_config_data_wait_loop_reg1 {
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struct {
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unsigned int wait_loop:16; /* [15:0] */
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unsigned int reserved:16; /* [31:16] */
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} bits;
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unsigned int u32;
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};
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struct dmcu *dce_dmcu_create(
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struct dc_context *ctx,
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const struct dce_dmcu_registers *regs,
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const struct dce_dmcu_shift *dmcu_shift,
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const struct dce_dmcu_mask *dmcu_mask);
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struct dmcu *dcn10_dmcu_create(
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struct dc_context *ctx,
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const struct dce_dmcu_registers *regs,
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const struct dce_dmcu_shift *dmcu_shift,
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const struct dce_dmcu_mask *dmcu_mask);
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void dce_dmcu_destroy(struct dmcu **dmcu);
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#endif /* _DCE_ABM_H_ */
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