cb83cece57
The only remaining use of the trampoline address by the trampoline itself is deriving the page table address from it, and this involves adding an offset of 0x0. So simplify this, and pass the new CR3 value directly. This makes the fact that the page table happens to be at the start of the trampoline allocation an implementation detail of the caller. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Link: https://lore.kernel.org/r/20230807162720.545787-15-ardb@kernel.org
18 lines
458 B
C
18 lines
458 B
C
#ifndef BOOT_COMPRESSED_PAGETABLE_H
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#define BOOT_COMPRESSED_PAGETABLE_H
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#define TRAMPOLINE_32BIT_SIZE (2 * PAGE_SIZE)
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#define TRAMPOLINE_32BIT_CODE_OFFSET PAGE_SIZE
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#define TRAMPOLINE_32BIT_CODE_SIZE 0xA0
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#ifndef __ASSEMBLER__
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extern unsigned long *trampoline_32bit;
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extern void trampoline_32bit_src(void *trampoline, bool enable_5lvl);
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extern const u16 trampoline_ljmp_imm_offset;
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#endif /* __ASSEMBLER__ */
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#endif /* BOOT_COMPRESSED_PAGETABLE_H */
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