33d7598d70
[why] "reference clock" is a very overloaded variable in DC and causes confusion as there are multiple sources of reference clock, which may be different values incorrect input values to DML will cause DCHUB to be programmed improperly and lead to hard to debug underflow issues [how] instead of using ref clock everywhere, specify WHICH ref clock: - xtalin - dccg refclk - dchub refclk these are all distinct values which may not be equal Signed-off-by: Jun Lei <Jun.Lei@amd.com> Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: David Francis <David.Francis@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
87 lines
2.4 KiB
C
87 lines
2.4 KiB
C
/*
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* Copyright 2012-15 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef __DAL_DCHUBBUB_H__
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#define __DAL_DCHUBBUB_H__
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enum dcc_control {
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dcc_control__256_256_xxx,
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dcc_control__128_128_xxx,
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dcc_control__256_64_64,
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};
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enum segment_order {
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segment_order__na,
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segment_order__contiguous,
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segment_order__non_contiguous,
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};
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struct dcn_hubbub_wm_set {
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uint32_t wm_set;
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uint32_t data_urgent;
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uint32_t pte_meta_urgent;
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uint32_t sr_enter;
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uint32_t sr_exit;
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uint32_t dram_clk_chanage;
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};
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struct dcn_hubbub_wm {
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struct dcn_hubbub_wm_set sets[4];
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};
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struct hubbub_funcs {
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void (*update_dchub)(
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struct hubbub *hubbub,
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struct dchub_init_data *dh_data);
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bool (*get_dcc_compression_cap)(struct hubbub *hubbub,
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const struct dc_dcc_surface_param *input,
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struct dc_surface_dcc_cap *output);
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bool (*dcc_support_swizzle)(
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enum swizzle_mode_values swizzle,
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unsigned int bytes_per_element,
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enum segment_order *segment_order_horz,
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enum segment_order *segment_order_vert);
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bool (*dcc_support_pixel_format)(
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enum surface_pixel_format format,
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unsigned int *bytes_per_element);
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void (*wm_read_state)(struct hubbub *hubbub,
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struct dcn_hubbub_wm *wm);
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void (*get_dchub_ref_freq)(struct hubbub *hubbub,
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unsigned int dccg_ref_freq_inKhz,
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unsigned int *dchub_ref_freq_inKhz);
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};
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struct hubbub {
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const struct hubbub_funcs *funcs;
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struct dc_context *ctx;
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};
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#endif
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