b79e8fd954
Create regs/xe_engine_regs.h file with all the registers and bit definitions used by the xe driver. Eventually the registers may be defined in a different way and since xe doesn't supported below gen12, the number of registers touched is much smaller, so create a new header. The definitions themselves are direct copy from the gt/intel_engine_regs.h file, just sorting the registers by address. Cleaning those up and adhering to a common coding style is left for later. Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
327 lines
13 KiB
C
327 lines
13 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2022 Intel Corporation
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*/
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#include "xe_wa.h"
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#include <linux/compiler_types.h>
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#include "regs/xe_engine_regs.h"
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#include "xe_device_types.h"
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#include "xe_force_wake.h"
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#include "xe_gt.h"
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#include "xe_hw_engine_types.h"
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#include "xe_mmio.h"
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#include "xe_platform_types.h"
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#include "xe_rtp.h"
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#include "xe_step.h"
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#include "gt/intel_gt_regs.h"
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#include "i915_reg.h"
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/**
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* DOC: Hardware workarounds
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*
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* Hardware workarounds are register programming documented to be executed in
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* the driver that fall outside of the normal programming sequences for a
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* platform. There are some basic categories of workarounds, depending on
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* how/when they are applied:
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*
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* - LRC workarounds: workarounds that touch registers that are
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* saved/restored to/from the HW context image. The list is emitted (via Load
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* Register Immediate commands) once when initializing the device and saved in
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* the default context. That default context is then used on every context
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* creation to have a "primed golden context", i.e. a context image that
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* already contains the changes needed to all the registers.
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*
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* - Engine workarounds: the list of these WAs is applied whenever the specific
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* engine is reset. It's also possible that a set of engine classes share a
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* common power domain and they are reset together. This happens on some
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* platforms with render and compute engines. In this case (at least) one of
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* them need to keeep the workaround programming: the approach taken in the
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* driver is to tie those workarounds to the first compute/render engine that
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* is registered. When executing with GuC submission, engine resets are
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* outside of kernel driver control, hence the list of registers involved in
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* written once, on engine initialization, and then passed to GuC, that
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* saves/restores their values before/after the reset takes place. See
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* ``drivers/gpu/drm/xe/xe_guc_ads.c`` for reference.
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*
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* - GT workarounds: the list of these WAs is applied whenever these registers
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* revert to their default values: on GPU reset, suspend/resume [1]_, etc.
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*
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* - Register whitelist: some workarounds need to be implemented in userspace,
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* but need to touch privileged registers. The whitelist in the kernel
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* instructs the hardware to allow the access to happen. From the kernel side,
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* this is just a special case of a MMIO workaround (as we write the list of
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* these to/be-whitelisted registers to some special HW registers).
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*
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* - Workaround batchbuffers: buffers that get executed automatically by the
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* hardware on every HW context restore. These buffers are created and
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* programmed in the default context so the hardware always go through those
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* programming sequences when switching contexts. The support for workaround
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* batchbuffers is enabled these hardware mechanisms:
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*
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* #. INDIRECT_CTX: A batchbuffer and an offset are provided in the default
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* context, pointing the hardware to jump to that location when that offset
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* is reached in the context restore. Workaround batchbuffer in the driver
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* currently uses this mechanism for all platforms.
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*
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* #. BB_PER_CTX_PTR: A batchbuffer is provided in the default context,
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* pointing the hardware to a buffer to continue executing after the
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* engine registers are restored in a context restore sequence. This is
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* currently not used in the driver.
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*
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* - Other: There are WAs that, due to their nature, cannot be applied from a
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* central place. Those are peppered around the rest of the code, as needed.
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* Workarounds related to the display IP are the main example.
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*
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* .. [1] Technically, some registers are powercontext saved & restored, so they
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* survive a suspend/resume. In practice, writing them again is not too
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* costly and simplifies things, so it's the approach taken in the driver.
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*
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* .. note::
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* Hardware workarounds in xe work the same way as in i915, with the
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* difference of how they are maintained in the code. In xe it uses the
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* xe_rtp infrastructure so the workarounds can be kept in tables, following
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* a more declarative approach rather than procedural.
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*/
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#undef _MMIO
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#undef MCR_REG
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#define _MMIO(x) _XE_RTP_REG(x)
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#define MCR_REG(x) _XE_RTP_MCR_REG(x)
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static bool match_14011060649(const struct xe_gt *gt,
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const struct xe_hw_engine *hwe)
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{
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return hwe->instance % 2 == 0;
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}
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static const struct xe_rtp_entry gt_was[] = {
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{ XE_RTP_NAME("14011060649"),
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XE_RTP_RULES(MEDIA_VERSION_RANGE(1200, 1255),
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ENGINE_CLASS(VIDEO_DECODE),
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FUNC(match_14011060649)),
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XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)),
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XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
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},
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{ XE_RTP_NAME("16010515920"),
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XE_RTP_RULES(SUBPLATFORM(DG2, G10),
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STEP(A0, B0),
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ENGINE_CLASS(VIDEO_DECODE)),
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XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F18(0), ALNUNIT_CLKGATE_DIS)),
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XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
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},
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{ XE_RTP_NAME("22010523718"),
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XE_RTP_RULES(SUBPLATFORM(DG2, G10)),
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XE_RTP_ACTIONS(SET(UNSLICE_UNIT_LEVEL_CLKGATE, CG3DDISCFEG_CLKGATE_DIS))
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},
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{ XE_RTP_NAME("14011006942"),
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XE_RTP_RULES(SUBPLATFORM(DG2, G10)),
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XE_RTP_ACTIONS(SET(GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE, DSS_ROUTER_CLKGATE_DIS))
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},
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{ XE_RTP_NAME("14010948348"),
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XE_RTP_RULES(SUBPLATFORM(DG2, G10), STEP(A0, B0)),
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XE_RTP_ACTIONS(SET(UNSLCGCTL9430, MSQDUNIT_CLKGATE_DIS))
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},
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{ XE_RTP_NAME("14011037102"),
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XE_RTP_RULES(SUBPLATFORM(DG2, G10), STEP(A0, B0)),
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XE_RTP_ACTIONS(SET(UNSLCGCTL9444, LTCDD_CLKGATE_DIS))
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},
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{ XE_RTP_NAME("14011371254"),
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XE_RTP_RULES(SUBPLATFORM(DG2, G10), STEP(A0, B0)),
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XE_RTP_ACTIONS(SET(GEN11_SLICE_UNIT_LEVEL_CLKGATE, NODEDSS_CLKGATE_DIS))
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},
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{ XE_RTP_NAME("14011431319"),
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XE_RTP_RULES(SUBPLATFORM(DG2, G10), STEP(A0, B0)),
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XE_RTP_ACTIONS(SET(UNSLCGCTL9440,
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GAMTLBOACS_CLKGATE_DIS |
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GAMTLBVDBOX7_CLKGATE_DIS | GAMTLBVDBOX6_CLKGATE_DIS |
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GAMTLBVDBOX5_CLKGATE_DIS | GAMTLBVDBOX4_CLKGATE_DIS |
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GAMTLBVDBOX3_CLKGATE_DIS | GAMTLBVDBOX2_CLKGATE_DIS |
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GAMTLBVDBOX1_CLKGATE_DIS | GAMTLBVDBOX0_CLKGATE_DIS |
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GAMTLBKCR_CLKGATE_DIS | GAMTLBGUC_CLKGATE_DIS |
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GAMTLBBLT_CLKGATE_DIS),
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SET(UNSLCGCTL9444,
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GAMTLBGFXA0_CLKGATE_DIS | GAMTLBGFXA1_CLKGATE_DIS |
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GAMTLBCOMPA0_CLKGATE_DIS | GAMTLBCOMPA1_CLKGATE_DIS |
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GAMTLBCOMPB0_CLKGATE_DIS | GAMTLBCOMPB1_CLKGATE_DIS |
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GAMTLBCOMPC0_CLKGATE_DIS | GAMTLBCOMPC1_CLKGATE_DIS |
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GAMTLBCOMPD0_CLKGATE_DIS | GAMTLBCOMPD1_CLKGATE_DIS |
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GAMTLBMERT_CLKGATE_DIS |
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GAMTLBVEBOX3_CLKGATE_DIS | GAMTLBVEBOX2_CLKGATE_DIS |
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GAMTLBVEBOX1_CLKGATE_DIS | GAMTLBVEBOX0_CLKGATE_DIS))
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},
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{ XE_RTP_NAME("14010569222"),
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XE_RTP_RULES(SUBPLATFORM(DG2, G10), STEP(A0, B0)),
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XE_RTP_ACTIONS(SET(UNSLICE_UNIT_LEVEL_CLKGATE, GAMEDIA_CLKGATE_DIS))
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},
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{ XE_RTP_NAME("14011028019"),
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XE_RTP_RULES(SUBPLATFORM(DG2, G10), STEP(A0, B0)),
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XE_RTP_ACTIONS(SET(SSMCGCTL9530, RTFUNIT_CLKGATE_DIS))
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},
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{ XE_RTP_NAME("14014830051"),
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XE_RTP_RULES(PLATFORM(DG2)),
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XE_RTP_ACTIONS(CLR(SARB_CHICKEN1, COMP_CKN_IN))
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},
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{ XE_RTP_NAME("14015795083"),
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XE_RTP_RULES(PLATFORM(DG2)),
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XE_RTP_ACTIONS(CLR(GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE))
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},
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{ XE_RTP_NAME("14011059788"),
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XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)),
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XE_RTP_ACTIONS(SET(GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE))
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},
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{ XE_RTP_NAME("1409420604"),
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XE_RTP_RULES(PLATFORM(DG1)),
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XE_RTP_ACTIONS(SET(SUBSLICE_UNIT_LEVEL_CLKGATE2, CPSSUNIT_CLKGATE_DIS))
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},
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{ XE_RTP_NAME("1408615072"),
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XE_RTP_RULES(PLATFORM(DG1)),
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XE_RTP_ACTIONS(SET(UNSLICE_UNIT_LEVEL_CLKGATE2, VSUNIT_CLKGATE_DIS_TGL))
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},
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{}
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};
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static const struct xe_rtp_entry engine_was[] = {
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{ XE_RTP_NAME("14015227452"),
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XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
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XE_RTP_ACTIONS(SET(GEN9_ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE,
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XE_RTP_ACTION_FLAG(MASKED_REG)))
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},
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{ XE_RTP_NAME("1606931601"),
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XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
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XE_RTP_ACTIONS(SET(GEN7_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ,
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XE_RTP_ACTION_FLAG(MASKED_REG)))
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},
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{ XE_RTP_NAME("22010931296, 18011464164, 14010919138"),
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XE_RTP_RULES(GRAPHICS_VERSION(1200), ENGINE_CLASS(RENDER)),
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XE_RTP_ACTIONS(SET(GEN7_FF_THREAD_MODE,
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GEN12_FF_TESSELATION_DOP_GATE_DISABLE))
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},
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{ XE_RTP_NAME("14010826681, 1606700617, 22010271021"),
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XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
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XE_RTP_ACTIONS(SET(GEN9_CS_DEBUG_MODE1, FF_DOP_CLOCK_GATE_DISABLE,
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XE_RTP_ACTION_FLAG(MASKED_REG)))
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},
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{ XE_RTP_NAME("18019627453"),
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XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
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XE_RTP_ACTIONS(SET(GEN9_CS_DEBUG_MODE1, FF_DOP_CLOCK_GATE_DISABLE,
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XE_RTP_ACTION_FLAG(MASKED_REG)))
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},
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{ XE_RTP_NAME("1409804808"),
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XE_RTP_RULES(GRAPHICS_VERSION(1200),
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ENGINE_CLASS(RENDER),
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IS_INTEGRATED),
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XE_RTP_ACTIONS(SET(GEN7_ROW_CHICKEN2, GEN12_PUSH_CONST_DEREF_HOLD_DIS,
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XE_RTP_ACTION_FLAG(MASKED_REG)))
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},
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{ XE_RTP_NAME("14010229206, 1409085225"),
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XE_RTP_RULES(GRAPHICS_VERSION(1200),
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ENGINE_CLASS(RENDER),
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IS_INTEGRATED),
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XE_RTP_ACTIONS(SET(GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH,
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XE_RTP_ACTION_FLAG(MASKED_REG)))
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},
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{ XE_RTP_NAME("1607297627, 1607030317, 1607186500"),
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XE_RTP_RULES(PLATFORM(TIGERLAKE), ENGINE_CLASS(RENDER)),
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XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE),
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GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
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GEN8_RC_SEMA_IDLE_MSG_DISABLE,
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XE_RTP_ACTION_FLAG(MASKED_REG)))
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},
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{ XE_RTP_NAME("1607297627, 1607030317, 1607186500"),
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XE_RTP_RULES(PLATFORM(ROCKETLAKE), ENGINE_CLASS(RENDER)),
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XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE),
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GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
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GEN8_RC_SEMA_IDLE_MSG_DISABLE,
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XE_RTP_ACTION_FLAG(MASKED_REG)))
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},
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{ XE_RTP_NAME("1406941453"),
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XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
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XE_RTP_ACTIONS(SET(GEN10_SAMPLER_MODE, ENABLE_SMALLPL,
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XE_RTP_ACTION_FLAG(MASKED_REG)))
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},
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{ XE_RTP_NAME("FtrPerCtxtPreemptionGranularityControl"),
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XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1250), ENGINE_CLASS(RENDER)),
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XE_RTP_ACTIONS(SET(GEN7_FF_SLICE_CS_CHICKEN1,
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GEN9_FFSC_PERCTX_PREEMPT_CTRL,
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XE_RTP_ACTION_FLAG(MASKED_REG)))
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},
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{}
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};
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static const struct xe_rtp_entry lrc_was[] = {
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{ XE_RTP_NAME("1409342910, 14010698770, 14010443199, 1408979724, 1409178076, 1409207793, 1409217633, 1409252684, 1409347922, 1409142259"),
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XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)),
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XE_RTP_ACTIONS(SET(GEN11_COMMON_SLICE_CHICKEN3,
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GEN12_DISABLE_CPS_AWARE_COLOR_PIPE,
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XE_RTP_ACTION_FLAG(MASKED_REG)))
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},
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{ XE_RTP_NAME("WaDisableGPGPUMidThreadPreemption"),
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XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)),
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XE_RTP_ACTIONS(FIELD_SET(GEN8_CS_CHICKEN1,
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GEN9_PREEMPT_GPGPU_LEVEL_MASK,
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GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL,
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XE_RTP_ACTION_FLAG(MASKED_REG)))
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},
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{ XE_RTP_NAME("16011163337"),
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XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)),
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/* read verification is ignored due to 1608008084. */
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XE_RTP_ACTIONS(FIELD_SET_NO_READ_MASK(GEN12_FF_MODE2,
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FF_MODE2_GS_TIMER_MASK,
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FF_MODE2_GS_TIMER_224))
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},
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{ XE_RTP_NAME("1409044764"),
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XE_RTP_RULES(PLATFORM(DG1)),
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XE_RTP_ACTIONS(CLR(GEN11_COMMON_SLICE_CHICKEN3,
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DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN,
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XE_RTP_ACTION_FLAG(MASKED_REG)))
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},
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{ XE_RTP_NAME("22010493298"),
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XE_RTP_RULES(PLATFORM(DG1)),
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XE_RTP_ACTIONS(SET(HIZ_CHICKEN,
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DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE,
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XE_RTP_ACTION_FLAG(MASKED_REG)))
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},
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{}
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};
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/**
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* xe_wa_process_gt - process GT workaround table
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* @gt: GT instance to process workarounds for
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*
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* Process GT workaround table for this platform, saving in @gt all the
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* workarounds that need to be applied at the GT level.
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*/
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void xe_wa_process_gt(struct xe_gt *gt)
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{
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xe_rtp_process(gt_was, >->reg_sr, gt, NULL);
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}
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/**
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* xe_wa_process_engine - process engine workaround table
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* @hwe: engine instance to process workarounds for
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*
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* Process engine workaround table for this platform, saving in @hwe all the
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* workarounds that need to be applied at the engine level that match this
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* engine.
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*/
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void xe_wa_process_engine(struct xe_hw_engine *hwe)
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{
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xe_rtp_process(engine_was, &hwe->reg_sr, hwe->gt, hwe);
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}
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/**
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* xe_wa_process_lrc - process context workaround table
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* @hwe: engine instance to process workarounds for
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*
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* Process context workaround table for this platform, saving in @hwe all the
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* workarounds that need to be applied on context restore. These are workarounds
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* touching registers that are part of the HW context image.
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*/
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void xe_wa_process_lrc(struct xe_hw_engine *hwe)
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{
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xe_rtp_process(lrc_was, &hwe->reg_lrc, hwe->gt, hwe);
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}
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