7e3a68be42
PC-Relative or PCREL addressing is an extension to the ELF ABI which uses Power ISA v3.1 PC-relative instructions to calculate addresses, rather than the traditional TOC scheme. Add an option to build vmlinux using pcrel addressing. Modules continue to use TOC addressing. - TOC address helpers and r2 are poisoned with -1 when running vmlinux. r2 could be used for something useful once things are ironed out. - Assembly must call C functions with @notoc annotation, or the linker complains aobut a missing nop after the call. This is done with the CFUNC macro introduced earlier. - Boot: with the exception of prom_init, the execution branches to the kernel virtual address early in boot, before any addresses are generated, which ensures 34-bit pcrel addressing does not miss the high PAGE_OFFSET bits. TOC relative addressing has a similar requirement. prom_init does not go to the virtual address and its addresses should not carry over to the post-prom kernel. - Ftrace trampolines are converted from TOC addressing to pcrel addressing, including module ftrace trampolines that currently use the kernel TOC to find ftrace target functions. - BPF function prologue and function calling generation are converted from TOC to pcrel. - copypage_64.S has an interesting problem, prefixed instructions have alignment restrictions so the linker can add padding, which makes the assembler treat the difference between two local labels as non-constant even if alignment is arranged so padding is not required. This may need toolchain help to solve nicely, for now move the prefix instruction out of the alternate patch section to work around it. This reduces kernel text size by about 6%. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://msgid.link/20230408021752.862660-6-npiggin@gmail.com
118 lines
2.1 KiB
ArmAsm
118 lines
2.1 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (C) 2008 Mark Nelson, IBM Corp.
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*/
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#include <asm/page.h>
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#include <asm/processor.h>
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#include <asm/ppc_asm.h>
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#include <asm/asm-offsets.h>
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#include <asm/export.h>
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#include <asm/feature-fixups.h>
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_GLOBAL_TOC(copy_page)
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BEGIN_FTR_SECTION
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lis r5,PAGE_SIZE@h
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FTR_SECTION_ELSE
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#ifdef CONFIG_PPC_BOOK3S_64
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b copypage_power7
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#endif
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ALT_FTR_SECTION_END_IFCLR(CPU_FTR_VMX_COPY)
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ori r5,r5,PAGE_SIZE@l
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#ifdef CONFIG_PPC_KERNEL_PCREL
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/*
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* Hack for toolchain - prefixed instructions cause label difference to
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* be non-constant even if 8 byte alignment is known, so they can not
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* be put in FTR sections.
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*/
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LOAD_REG_ADDR(r10, ppc64_caches)
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BEGIN_FTR_SECTION
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#else
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BEGIN_FTR_SECTION
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LOAD_REG_ADDR(r10, ppc64_caches)
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#endif
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lwz r11,DCACHEL1LOGBLOCKSIZE(r10) /* log2 of cache block size */
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lwz r12,DCACHEL1BLOCKSIZE(r10) /* get cache block size */
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li r9,0
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srd r8,r5,r11
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mtctr r8
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.Lsetup:
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dcbt r9,r4
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dcbz r9,r3
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add r9,r9,r12
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bdnz .Lsetup
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END_FTR_SECTION_IFSET(CPU_FTR_CP_USE_DCBTZ)
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addi r3,r3,-8
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srdi r8,r5,7 /* page is copied in 128 byte strides */
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addi r8,r8,-1 /* one stride copied outside loop */
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mtctr r8
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ld r5,0(r4)
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ld r6,8(r4)
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ld r7,16(r4)
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ldu r8,24(r4)
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1: std r5,8(r3)
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std r6,16(r3)
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ld r9,8(r4)
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ld r10,16(r4)
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std r7,24(r3)
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std r8,32(r3)
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ld r11,24(r4)
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ld r12,32(r4)
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std r9,40(r3)
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std r10,48(r3)
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ld r5,40(r4)
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ld r6,48(r4)
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std r11,56(r3)
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std r12,64(r3)
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ld r7,56(r4)
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ld r8,64(r4)
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std r5,72(r3)
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std r6,80(r3)
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ld r9,72(r4)
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ld r10,80(r4)
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std r7,88(r3)
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std r8,96(r3)
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ld r11,88(r4)
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ld r12,96(r4)
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std r9,104(r3)
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std r10,112(r3)
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ld r5,104(r4)
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ld r6,112(r4)
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std r11,120(r3)
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stdu r12,128(r3)
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ld r7,120(r4)
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ldu r8,128(r4)
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bdnz 1b
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std r5,8(r3)
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std r6,16(r3)
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ld r9,8(r4)
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ld r10,16(r4)
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std r7,24(r3)
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std r8,32(r3)
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ld r11,24(r4)
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ld r12,32(r4)
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std r9,40(r3)
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std r10,48(r3)
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ld r5,40(r4)
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ld r6,48(r4)
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std r11,56(r3)
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std r12,64(r3)
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ld r7,56(r4)
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ld r8,64(r4)
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std r5,72(r3)
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std r6,80(r3)
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ld r9,72(r4)
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ld r10,80(r4)
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std r7,88(r3)
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std r8,96(r3)
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ld r11,88(r4)
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ld r12,96(r4)
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std r9,104(r3)
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std r10,112(r3)
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std r11,120(r3)
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std r12,128(r3)
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blr
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EXPORT_SYMBOL(copy_page)
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