1a59d1b8e0
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not write to the free software foundation inc 59 temple place suite 330 boston ma 02111 1307 usa extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 1334 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Richard Fontana <rfontana@redhat.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070033.113240726@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
461 lines
17 KiB
C
461 lines
17 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/* *********************************************************************
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* SB1250 Board Support Package
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*
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* Generic Bus Constants File: sb1250_genbus.h
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*
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* This module contains constants and macros useful for
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* manipulating the SB1250's Generic Bus interface
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*
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* SB1250 specification level: User's manual 10/21/02
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* BCM1280 specification level: User's Manual 11/14/03
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*
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*********************************************************************
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*
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* Copyright 2000, 2001, 2002, 2003
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* Broadcom Corporation. All rights reserved.
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*
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********************************************************************* */
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#ifndef _SB1250_GENBUS_H
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#define _SB1250_GENBUS_H
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#include <asm/sibyte/sb1250_defs.h>
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/*
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* Generic Bus Region Configuration Registers (Table 11-4)
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*/
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#define S_IO_RDY_ACTIVE 0
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#define M_IO_RDY_ACTIVE _SB_MAKEMASK1(S_IO_RDY_ACTIVE)
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#define S_IO_ENA_RDY 1
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#define M_IO_ENA_RDY _SB_MAKEMASK1(S_IO_ENA_RDY)
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#define S_IO_WIDTH_SEL 2
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#define M_IO_WIDTH_SEL _SB_MAKEMASK(2, S_IO_WIDTH_SEL)
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#define K_IO_WIDTH_SEL_1 0
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#define K_IO_WIDTH_SEL_2 1
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#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \
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|| SIBYTE_HDR_FEATURE_CHIP(1480)
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#define K_IO_WIDTH_SEL_1L 2
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#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
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#define K_IO_WIDTH_SEL_4 3
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#define V_IO_WIDTH_SEL(x) _SB_MAKEVALUE(x, S_IO_WIDTH_SEL)
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#define G_IO_WIDTH_SEL(x) _SB_GETVALUE(x, S_IO_WIDTH_SEL, M_IO_WIDTH_SEL)
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#define S_IO_PARITY_ENA 4
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#define M_IO_PARITY_ENA _SB_MAKEMASK1(S_IO_PARITY_ENA)
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#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \
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|| SIBYTE_HDR_FEATURE_CHIP(1480)
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#define S_IO_BURST_EN 5
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#define M_IO_BURST_EN _SB_MAKEMASK1(S_IO_BURST_EN)
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#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
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#define S_IO_PARITY_ODD 6
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#define M_IO_PARITY_ODD _SB_MAKEMASK1(S_IO_PARITY_ODD)
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#define S_IO_NONMUX 7
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#define M_IO_NONMUX _SB_MAKEMASK1(S_IO_NONMUX)
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#define S_IO_TIMEOUT 8
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#define M_IO_TIMEOUT _SB_MAKEMASK(8, S_IO_TIMEOUT)
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#define V_IO_TIMEOUT(x) _SB_MAKEVALUE(x, S_IO_TIMEOUT)
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#define G_IO_TIMEOUT(x) _SB_GETVALUE(x, S_IO_TIMEOUT, M_IO_TIMEOUT)
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/*
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* Generic Bus Region Size register (Table 11-5)
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*/
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#define S_IO_MULT_SIZE 0
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#define M_IO_MULT_SIZE _SB_MAKEMASK(12, S_IO_MULT_SIZE)
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#define V_IO_MULT_SIZE(x) _SB_MAKEVALUE(x, S_IO_MULT_SIZE)
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#define G_IO_MULT_SIZE(x) _SB_GETVALUE(x, S_IO_MULT_SIZE, M_IO_MULT_SIZE)
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#define S_IO_REGSIZE 16 /* # bits to shift size for this reg */
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/*
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* Generic Bus Region Address (Table 11-6)
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*/
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#define S_IO_START_ADDR 0
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#define M_IO_START_ADDR _SB_MAKEMASK(14, S_IO_START_ADDR)
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#define V_IO_START_ADDR(x) _SB_MAKEVALUE(x, S_IO_START_ADDR)
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#define G_IO_START_ADDR(x) _SB_GETVALUE(x, S_IO_START_ADDR, M_IO_START_ADDR)
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#define S_IO_ADDRBASE 16 /* # bits to shift addr for this reg */
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#define M_IO_BLK_CACHE _SB_MAKEMASK1(15)
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/*
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* Generic Bus Timing 0 Registers (Table 11-7)
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*/
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#define S_IO_ALE_WIDTH 0
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#define M_IO_ALE_WIDTH _SB_MAKEMASK(3, S_IO_ALE_WIDTH)
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#define V_IO_ALE_WIDTH(x) _SB_MAKEVALUE(x, S_IO_ALE_WIDTH)
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#define G_IO_ALE_WIDTH(x) _SB_GETVALUE(x, S_IO_ALE_WIDTH, M_IO_ALE_WIDTH)
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#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \
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|| SIBYTE_HDR_FEATURE_CHIP(1480)
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#define M_IO_EARLY_CS _SB_MAKEMASK1(3)
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#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
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#define S_IO_ALE_TO_CS 4
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#define M_IO_ALE_TO_CS _SB_MAKEMASK(2, S_IO_ALE_TO_CS)
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#define V_IO_ALE_TO_CS(x) _SB_MAKEVALUE(x, S_IO_ALE_TO_CS)
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#define G_IO_ALE_TO_CS(x) _SB_GETVALUE(x, S_IO_ALE_TO_CS, M_IO_ALE_TO_CS)
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#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \
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|| SIBYTE_HDR_FEATURE_CHIP(1480)
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#define S_IO_BURST_WIDTH _SB_MAKE64(6)
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#define M_IO_BURST_WIDTH _SB_MAKEMASK(2, S_IO_BURST_WIDTH)
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#define V_IO_BURST_WIDTH(x) _SB_MAKEVALUE(x, S_IO_BURST_WIDTH)
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#define G_IO_BURST_WIDTH(x) _SB_GETVALUE(x, S_IO_BURST_WIDTH, M_IO_BURST_WIDTH)
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#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
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#define S_IO_CS_WIDTH 8
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#define M_IO_CS_WIDTH _SB_MAKEMASK(5, S_IO_CS_WIDTH)
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#define V_IO_CS_WIDTH(x) _SB_MAKEVALUE(x, S_IO_CS_WIDTH)
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#define G_IO_CS_WIDTH(x) _SB_GETVALUE(x, S_IO_CS_WIDTH, M_IO_CS_WIDTH)
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#define S_IO_RDY_SMPLE 13
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#define M_IO_RDY_SMPLE _SB_MAKEMASK(3, S_IO_RDY_SMPLE)
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#define V_IO_RDY_SMPLE(x) _SB_MAKEVALUE(x, S_IO_RDY_SMPLE)
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#define G_IO_RDY_SMPLE(x) _SB_GETVALUE(x, S_IO_RDY_SMPLE, M_IO_RDY_SMPLE)
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/*
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* Generic Bus Timing 1 Registers (Table 11-8)
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*/
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#define S_IO_ALE_TO_WRITE 0
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#define M_IO_ALE_TO_WRITE _SB_MAKEMASK(3, S_IO_ALE_TO_WRITE)
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#define V_IO_ALE_TO_WRITE(x) _SB_MAKEVALUE(x, S_IO_ALE_TO_WRITE)
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#define G_IO_ALE_TO_WRITE(x) _SB_GETVALUE(x, S_IO_ALE_TO_WRITE, M_IO_ALE_TO_WRITE)
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#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \
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|| SIBYTE_HDR_FEATURE_CHIP(1480)
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#define M_IO_RDY_SYNC _SB_MAKEMASK1(3)
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#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
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#define S_IO_WRITE_WIDTH 4
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#define M_IO_WRITE_WIDTH _SB_MAKEMASK(4, S_IO_WRITE_WIDTH)
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#define V_IO_WRITE_WIDTH(x) _SB_MAKEVALUE(x, S_IO_WRITE_WIDTH)
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#define G_IO_WRITE_WIDTH(x) _SB_GETVALUE(x, S_IO_WRITE_WIDTH, M_IO_WRITE_WIDTH)
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#define S_IO_IDLE_CYCLE 8
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#define M_IO_IDLE_CYCLE _SB_MAKEMASK(4, S_IO_IDLE_CYCLE)
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#define V_IO_IDLE_CYCLE(x) _SB_MAKEVALUE(x, S_IO_IDLE_CYCLE)
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#define G_IO_IDLE_CYCLE(x) _SB_GETVALUE(x, S_IO_IDLE_CYCLE, M_IO_IDLE_CYCLE)
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#define S_IO_OE_TO_CS 12
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#define M_IO_OE_TO_CS _SB_MAKEMASK(2, S_IO_OE_TO_CS)
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#define V_IO_OE_TO_CS(x) _SB_MAKEVALUE(x, S_IO_OE_TO_CS)
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#define G_IO_OE_TO_CS(x) _SB_GETVALUE(x, S_IO_OE_TO_CS, M_IO_OE_TO_CS)
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#define S_IO_CS_TO_OE 14
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#define M_IO_CS_TO_OE _SB_MAKEMASK(2, S_IO_CS_TO_OE)
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#define V_IO_CS_TO_OE(x) _SB_MAKEVALUE(x, S_IO_CS_TO_OE)
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#define G_IO_CS_TO_OE(x) _SB_GETVALUE(x, S_IO_CS_TO_OE, M_IO_CS_TO_OE)
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/*
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* Generic Bus Interrupt Status Register (Table 11-9)
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*/
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#define M_IO_CS_ERR_INT _SB_MAKEMASK(0, 8)
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#define M_IO_CS0_ERR_INT _SB_MAKEMASK1(0)
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#define M_IO_CS1_ERR_INT _SB_MAKEMASK1(1)
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#define M_IO_CS2_ERR_INT _SB_MAKEMASK1(2)
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#define M_IO_CS3_ERR_INT _SB_MAKEMASK1(3)
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#define M_IO_CS4_ERR_INT _SB_MAKEMASK1(4)
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#define M_IO_CS5_ERR_INT _SB_MAKEMASK1(5)
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#define M_IO_CS6_ERR_INT _SB_MAKEMASK1(6)
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#define M_IO_CS7_ERR_INT _SB_MAKEMASK1(7)
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#define M_IO_RD_PAR_INT _SB_MAKEMASK1(9)
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#define M_IO_TIMEOUT_INT _SB_MAKEMASK1(10)
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#define M_IO_ILL_ADDR_INT _SB_MAKEMASK1(11)
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#define M_IO_MULT_CS_INT _SB_MAKEMASK1(12)
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#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
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#define M_IO_COH_ERR _SB_MAKEMASK1(14)
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#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
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/*
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* Generic Bus Output Drive Control Register 0 (Table 14-18)
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*/
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#define S_IO_SLEW0 0
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#define M_IO_SLEW0 _SB_MAKEMASK(2, S_IO_SLEW0)
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#define V_IO_SLEW0(x) _SB_MAKEVALUE(x, S_IO_SLEW0)
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#define G_IO_SLEW0(x) _SB_GETVALUE(x, S_IO_SLEW0, M_IO_SLEW0)
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#define S_IO_DRV_A 2
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#define M_IO_DRV_A _SB_MAKEMASK(2, S_IO_DRV_A)
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#define V_IO_DRV_A(x) _SB_MAKEVALUE(x, S_IO_DRV_A)
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#define G_IO_DRV_A(x) _SB_GETVALUE(x, S_IO_DRV_A, M_IO_DRV_A)
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#define S_IO_DRV_B 6
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#define M_IO_DRV_B _SB_MAKEMASK(2, S_IO_DRV_B)
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#define V_IO_DRV_B(x) _SB_MAKEVALUE(x, S_IO_DRV_B)
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#define G_IO_DRV_B(x) _SB_GETVALUE(x, S_IO_DRV_B, M_IO_DRV_B)
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#define S_IO_DRV_C 10
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#define M_IO_DRV_C _SB_MAKEMASK(2, S_IO_DRV_C)
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#define V_IO_DRV_C(x) _SB_MAKEVALUE(x, S_IO_DRV_C)
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#define G_IO_DRV_C(x) _SB_GETVALUE(x, S_IO_DRV_C, M_IO_DRV_C)
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#define S_IO_DRV_D 14
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#define M_IO_DRV_D _SB_MAKEMASK(2, S_IO_DRV_D)
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#define V_IO_DRV_D(x) _SB_MAKEVALUE(x, S_IO_DRV_D)
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#define G_IO_DRV_D(x) _SB_GETVALUE(x, S_IO_DRV_D, M_IO_DRV_D)
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/*
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* Generic Bus Output Drive Control Register 1 (Table 14-19)
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*/
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#define S_IO_DRV_E 2
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#define M_IO_DRV_E _SB_MAKEMASK(2, S_IO_DRV_E)
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#define V_IO_DRV_E(x) _SB_MAKEVALUE(x, S_IO_DRV_E)
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#define G_IO_DRV_E(x) _SB_GETVALUE(x, S_IO_DRV_E, M_IO_DRV_E)
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#define S_IO_DRV_F 6
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#define M_IO_DRV_F _SB_MAKEMASK(2, S_IO_DRV_F)
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#define V_IO_DRV_F(x) _SB_MAKEVALUE(x, S_IO_DRV_F)
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#define G_IO_DRV_F(x) _SB_GETVALUE(x, S_IO_DRV_F, M_IO_DRV_F)
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#define S_IO_SLEW1 8
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#define M_IO_SLEW1 _SB_MAKEMASK(2, S_IO_SLEW1)
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#define V_IO_SLEW1(x) _SB_MAKEVALUE(x, S_IO_SLEW1)
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#define G_IO_SLEW1(x) _SB_GETVALUE(x, S_IO_SLEW1, M_IO_SLEW1)
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#define S_IO_DRV_G 10
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#define M_IO_DRV_G _SB_MAKEMASK(2, S_IO_DRV_G)
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#define V_IO_DRV_G(x) _SB_MAKEVALUE(x, S_IO_DRV_G)
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#define G_IO_DRV_G(x) _SB_GETVALUE(x, S_IO_DRV_G, M_IO_DRV_G)
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#define S_IO_SLEW2 12
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#define M_IO_SLEW2 _SB_MAKEMASK(2, S_IO_SLEW2)
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#define V_IO_SLEW2(x) _SB_MAKEVALUE(x, S_IO_SLEW2)
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#define G_IO_SLEW2(x) _SB_GETVALUE(x, S_IO_SLEW2, M_IO_SLEW2)
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#define S_IO_DRV_H 14
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#define M_IO_DRV_H _SB_MAKEMASK(2, S_IO_DRV_H)
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#define V_IO_DRV_H(x) _SB_MAKEVALUE(x, S_IO_DRV_H)
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#define G_IO_DRV_H(x) _SB_GETVALUE(x, S_IO_DRV_H, M_IO_DRV_H)
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/*
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* Generic Bus Output Drive Control Register 2 (Table 14-20)
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*/
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#define S_IO_DRV_J 2
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#define M_IO_DRV_J _SB_MAKEMASK(2, S_IO_DRV_J)
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#define V_IO_DRV_J(x) _SB_MAKEVALUE(x, S_IO_DRV_J)
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#define G_IO_DRV_J(x) _SB_GETVALUE(x, S_IO_DRV_J, M_IO_DRV_J)
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#define S_IO_DRV_K 6
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#define M_IO_DRV_K _SB_MAKEMASK(2, S_IO_DRV_K)
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#define V_IO_DRV_K(x) _SB_MAKEVALUE(x, S_IO_DRV_K)
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#define G_IO_DRV_K(x) _SB_GETVALUE(x, S_IO_DRV_K, M_IO_DRV_K)
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#define S_IO_DRV_L 10
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#define M_IO_DRV_L _SB_MAKEMASK(2, S_IO_DRV_L)
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#define V_IO_DRV_L(x) _SB_MAKEVALUE(x, S_IO_DRV_L)
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#define G_IO_DRV_L(x) _SB_GETVALUE(x, S_IO_DRV_L, M_IO_DRV_L)
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#define S_IO_DRV_M 14
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#define M_IO_DRV_M _SB_MAKEMASK(2, S_IO_DRV_M)
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#define V_IO_DRV_M(x) _SB_MAKEVALUE(x, S_IO_DRV_M)
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#define G_IO_DRV_M(x) _SB_GETVALUE(x, S_IO_DRV_M, M_IO_DRV_M)
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/*
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* Generic Bus Output Drive Control Register 3 (Table 14-21)
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*/
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#define S_IO_SLEW3 0
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#define M_IO_SLEW3 _SB_MAKEMASK(2, S_IO_SLEW3)
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#define V_IO_SLEW3(x) _SB_MAKEVALUE(x, S_IO_SLEW3)
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#define G_IO_SLEW3(x) _SB_GETVALUE(x, S_IO_SLEW3, M_IO_SLEW3)
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#define S_IO_DRV_N 2
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#define M_IO_DRV_N _SB_MAKEMASK(2, S_IO_DRV_N)
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#define V_IO_DRV_N(x) _SB_MAKEVALUE(x, S_IO_DRV_N)
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#define G_IO_DRV_N(x) _SB_GETVALUE(x, S_IO_DRV_N, M_IO_DRV_N)
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#define S_IO_DRV_P 6
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#define M_IO_DRV_P _SB_MAKEMASK(2, S_IO_DRV_P)
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#define V_IO_DRV_P(x) _SB_MAKEVALUE(x, S_IO_DRV_P)
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#define G_IO_DRV_P(x) _SB_GETVALUE(x, S_IO_DRV_P, M_IO_DRV_P)
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#define S_IO_DRV_Q 10
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#define M_IO_DRV_Q _SB_MAKEMASK(2, S_IO_DRV_Q)
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#define V_IO_DRV_Q(x) _SB_MAKEVALUE(x, S_IO_DRV_Q)
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#define G_IO_DRV_Q(x) _SB_GETVALUE(x, S_IO_DRV_Q, M_IO_DRV_Q)
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#define S_IO_DRV_R 14
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#define M_IO_DRV_R _SB_MAKEMASK(2, S_IO_DRV_R)
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#define V_IO_DRV_R(x) _SB_MAKEVALUE(x, S_IO_DRV_R)
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#define G_IO_DRV_R(x) _SB_GETVALUE(x, S_IO_DRV_R, M_IO_DRV_R)
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/*
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* PCMCIA configuration register (Table 12-6)
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*/
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#define M_PCMCIA_CFG_ATTRMEM _SB_MAKEMASK1(0)
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#define M_PCMCIA_CFG_3VEN _SB_MAKEMASK1(1)
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#define M_PCMCIA_CFG_5VEN _SB_MAKEMASK1(2)
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#define M_PCMCIA_CFG_VPPEN _SB_MAKEMASK1(3)
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#define M_PCMCIA_CFG_RESET _SB_MAKEMASK1(4)
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#define M_PCMCIA_CFG_APWRONEN _SB_MAKEMASK1(5)
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#define M_PCMCIA_CFG_CDMASK _SB_MAKEMASK1(6)
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#define M_PCMCIA_CFG_WPMASK _SB_MAKEMASK1(7)
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#define M_PCMCIA_CFG_RDYMASK _SB_MAKEMASK1(8)
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#define M_PCMCIA_CFG_PWRCTL _SB_MAKEMASK1(9)
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#if SIBYTE_HDR_FEATURE_CHIP(1480)
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#define S_PCMCIA_MODE 16
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#define M_PCMCIA_MODE _SB_MAKEMASK(3, S_PCMCIA_MODE)
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#define V_PCMCIA_MODE(x) _SB_MAKEVALUE(x, S_PCMCIA_MODE)
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#define G_PCMCIA_MODE(x) _SB_GETVALUE(x, S_PCMCIA_MODE, M_PCMCIA_MODE)
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#define K_PCMCIA_MODE_PCMA_NOB 0 /* standard PCMCIA "A", no "B" */
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#define K_PCMCIA_MODE_IDEA_NOB 1 /* IDE "A", no "B" */
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#define K_PCMCIA_MODE_PCMIOA_NOB 2 /* PCMCIA with I/O "A", no "B" */
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#define K_PCMCIA_MODE_PCMA_PCMB 4 /* standard PCMCIA "A", standard PCMCIA "B" */
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#define K_PCMCIA_MODE_IDEA_PCMB 5 /* IDE "A", standard PCMCIA "B" */
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#define K_PCMCIA_MODE_PCMA_IDEB 6 /* standard PCMCIA "A", IDE "B" */
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#define K_PCMCIA_MODE_IDEA_IDEB 7 /* IDE "A", IDE "B" */
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#endif
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/*
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* PCMCIA status register (Table 12-7)
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*/
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#define M_PCMCIA_STATUS_CD1 _SB_MAKEMASK1(0)
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#define M_PCMCIA_STATUS_CD2 _SB_MAKEMASK1(1)
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#define M_PCMCIA_STATUS_VS1 _SB_MAKEMASK1(2)
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#define M_PCMCIA_STATUS_VS2 _SB_MAKEMASK1(3)
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#define M_PCMCIA_STATUS_WP _SB_MAKEMASK1(4)
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#define M_PCMCIA_STATUS_RDY _SB_MAKEMASK1(5)
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#define M_PCMCIA_STATUS_3VEN _SB_MAKEMASK1(6)
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#define M_PCMCIA_STATUS_5VEN _SB_MAKEMASK1(7)
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#define M_PCMCIA_STATUS_CDCHG _SB_MAKEMASK1(8)
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#define M_PCMCIA_STATUS_WPCHG _SB_MAKEMASK1(9)
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#define M_PCMCIA_STATUS_RDYCHG _SB_MAKEMASK1(10)
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/*
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* GPIO Interrupt Type Register (table 13-3)
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*/
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#define K_GPIO_INTR_DISABLE 0
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#define K_GPIO_INTR_EDGE 1
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#define K_GPIO_INTR_LEVEL 2
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#define K_GPIO_INTR_SPLIT 3
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#define S_GPIO_INTR_TYPEX(n) (((n)/2)*2)
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#define M_GPIO_INTR_TYPEX(n) _SB_MAKEMASK(2, S_GPIO_INTR_TYPEX(n))
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#define V_GPIO_INTR_TYPEX(n, x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPEX(n))
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#define G_GPIO_INTR_TYPEX(n, x) _SB_GETVALUE(x, S_GPIO_INTR_TYPEX(n), M_GPIO_INTR_TYPEX(n))
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#define S_GPIO_INTR_TYPE0 0
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#define M_GPIO_INTR_TYPE0 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE0)
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#define V_GPIO_INTR_TYPE0(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE0)
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#define G_GPIO_INTR_TYPE0(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE0, M_GPIO_INTR_TYPE0)
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#define S_GPIO_INTR_TYPE2 2
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#define M_GPIO_INTR_TYPE2 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE2)
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#define V_GPIO_INTR_TYPE2(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE2)
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#define G_GPIO_INTR_TYPE2(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE2, M_GPIO_INTR_TYPE2)
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#define S_GPIO_INTR_TYPE4 4
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#define M_GPIO_INTR_TYPE4 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE4)
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#define V_GPIO_INTR_TYPE4(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE4)
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#define G_GPIO_INTR_TYPE4(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE4, M_GPIO_INTR_TYPE4)
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#define S_GPIO_INTR_TYPE6 6
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#define M_GPIO_INTR_TYPE6 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE6)
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#define V_GPIO_INTR_TYPE6(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE6)
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#define G_GPIO_INTR_TYPE6(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE6, M_GPIO_INTR_TYPE6)
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#define S_GPIO_INTR_TYPE8 8
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#define M_GPIO_INTR_TYPE8 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE8)
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#define V_GPIO_INTR_TYPE8(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE8)
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#define G_GPIO_INTR_TYPE8(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE8, M_GPIO_INTR_TYPE8)
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#define S_GPIO_INTR_TYPE10 10
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#define M_GPIO_INTR_TYPE10 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE10)
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#define V_GPIO_INTR_TYPE10(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE10)
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#define G_GPIO_INTR_TYPE10(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE10, M_GPIO_INTR_TYPE10)
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#define S_GPIO_INTR_TYPE12 12
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#define M_GPIO_INTR_TYPE12 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE12)
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#define V_GPIO_INTR_TYPE12(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE12)
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#define G_GPIO_INTR_TYPE12(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE12, M_GPIO_INTR_TYPE12)
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#define S_GPIO_INTR_TYPE14 14
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#define M_GPIO_INTR_TYPE14 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE14)
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#define V_GPIO_INTR_TYPE14(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE14)
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#define G_GPIO_INTR_TYPE14(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE14, M_GPIO_INTR_TYPE14)
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#if SIBYTE_HDR_FEATURE_CHIP(1480)
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/*
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* GPIO Interrupt Additional Type Register
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*/
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#define K_GPIO_INTR_BOTHEDGE 0
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#define K_GPIO_INTR_RISEEDGE 1
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#define K_GPIO_INTR_UNPRED1 2
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#define K_GPIO_INTR_UNPRED2 3
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#define S_GPIO_INTR_ATYPEX(n) (((n)/2)*2)
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#define M_GPIO_INTR_ATYPEX(n) _SB_MAKEMASK(2, S_GPIO_INTR_ATYPEX(n))
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#define V_GPIO_INTR_ATYPEX(n, x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPEX(n))
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#define G_GPIO_INTR_ATYPEX(n, x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPEX(n), M_GPIO_INTR_ATYPEX(n))
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#define S_GPIO_INTR_ATYPE0 0
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#define M_GPIO_INTR_ATYPE0 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE0)
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#define V_GPIO_INTR_ATYPE0(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE0)
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#define G_GPIO_INTR_ATYPE0(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE0, M_GPIO_INTR_ATYPE0)
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#define S_GPIO_INTR_ATYPE2 2
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#define M_GPIO_INTR_ATYPE2 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE2)
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#define V_GPIO_INTR_ATYPE2(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE2)
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#define G_GPIO_INTR_ATYPE2(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE2, M_GPIO_INTR_ATYPE2)
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#define S_GPIO_INTR_ATYPE4 4
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#define M_GPIO_INTR_ATYPE4 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE4)
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#define V_GPIO_INTR_ATYPE4(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE4)
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#define G_GPIO_INTR_ATYPE4(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE4, M_GPIO_INTR_ATYPE4)
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#define S_GPIO_INTR_ATYPE6 6
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#define M_GPIO_INTR_ATYPE6 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE6)
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#define V_GPIO_INTR_ATYPE6(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE6)
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#define G_GPIO_INTR_ATYPE6(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE6, M_GPIO_INTR_ATYPE6)
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#define S_GPIO_INTR_ATYPE8 8
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#define M_GPIO_INTR_ATYPE8 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE8)
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#define V_GPIO_INTR_ATYPE8(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE8)
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#define G_GPIO_INTR_ATYPE8(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE8, M_GPIO_INTR_ATYPE8)
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#define S_GPIO_INTR_ATYPE10 10
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#define M_GPIO_INTR_ATYPE10 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE10)
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#define V_GPIO_INTR_ATYPE10(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE10)
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#define G_GPIO_INTR_ATYPE10(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE10, M_GPIO_INTR_ATYPE10)
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#define S_GPIO_INTR_ATYPE12 12
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#define M_GPIO_INTR_ATYPE12 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE12)
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#define V_GPIO_INTR_ATYPE12(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE12)
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#define G_GPIO_INTR_ATYPE12(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE12, M_GPIO_INTR_ATYPE12)
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#define S_GPIO_INTR_ATYPE14 14
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#define M_GPIO_INTR_ATYPE14 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE14)
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#define V_GPIO_INTR_ATYPE14(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE14)
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#define G_GPIO_INTR_ATYPE14(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE14, M_GPIO_INTR_ATYPE14)
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#endif
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#endif
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