a2b36ffbf5
This reverts commit4c5e242d3e. Prior to4c5e242d3e("x86/PCI: Clip only host bridge windows for E820 regions"), E820 regions did not affect PCI host bridge windows. We only looked at E820 regions and avoided them when allocating new MMIO space. If firmware PCI bridge window and BAR assignments used E820 regions, we left them alone. After4c5e242d3e, we removed E820 regions from the PCI host bridge windows before looking at BARs, so firmware assignments in E820 regions looked like errors, and we moved things around to fit in the space left (if any) after removing the E820 regions. This unnecessary BAR reassignment broke several machines. Guilherme reported that Steam Deck fails to boot after4c5e242d3e. We clipped the window that contained most 32-bit BARs: BIOS-e820: [mem 0x00000000a0000000-0x00000000a00fffff] reserved acpi PNP0A08:00: clipped [mem 0x80000000-0xf7ffffff window] to [mem 0xa0100000-0xf7ffffff window] for e820 entry [mem 0xa0000000-0xa00fffff] which forced us to reassign all those BARs, for example, this NVMe BAR: pci 0000:00:01.2: PCI bridge to [bus 01] pci 0000:00:01.2: bridge window [mem 0x80600000-0x806fffff] pci 0000:01:00.0: BAR 0: [mem 0x80600000-0x80603fff 64bit] pci 0000:00:01.2: can't claim window [mem 0x80600000-0x806fffff]: no compatible bridge window pci 0000:01:00.0: can't claim BAR 0 [mem 0x80600000-0x80603fff 64bit]: no compatible bridge window pci 0000:00:01.2: bridge window: assigned [mem 0xa0100000-0xa01fffff] pci 0000:01:00.0: BAR 0: assigned [mem 0xa0100000-0xa0103fff 64bit] All the reassignments were successful, so the devices should have been functional at the new addresses, but some were not. Andy reported a similar failure on an Intel MID platform. Benjamin reported a similar failure on a VMWare Fusion VM. Note: this is not a clean revert; this revert keeps the later change to make the clipping dependent on a new pci_use_e820 bool, moving the checking of this bool to arch_remove_reservations(). [bhelgaas: commit log, add more reporters and testers] BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=216109 Reported-by: Guilherme G. Piccoli <gpiccoli@igalia.com> Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reported-by: Benjamin Coddington <bcodding@redhat.com> Reported-by: Jongman Heo <jongman.heo@gmail.com> Fixes:4c5e242d3e("x86/PCI: Clip only host bridge windows for E820 regions") Link: https://lore.kernel.org/r/20220612144325.85366-1-hdegoede@redhat.com Tested-by: Guilherme G. Piccoli <gpiccoli@igalia.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Tested-by: Benjamin Coddington <bcodding@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
55 lines
1.9 KiB
C
55 lines
1.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_E820_API_H
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#define _ASM_E820_API_H
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#include <asm/e820/types.h>
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extern struct e820_table *e820_table;
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extern struct e820_table *e820_table_kexec;
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extern struct e820_table *e820_table_firmware;
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extern unsigned long pci_mem_start;
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extern bool e820__mapped_raw_any(u64 start, u64 end, enum e820_type type);
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extern bool e820__mapped_any(u64 start, u64 end, enum e820_type type);
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extern bool e820__mapped_all(u64 start, u64 end, enum e820_type type);
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extern void e820__range_add (u64 start, u64 size, enum e820_type type);
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extern u64 e820__range_update(u64 start, u64 size, enum e820_type old_type, enum e820_type new_type);
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extern u64 e820__range_remove(u64 start, u64 size, enum e820_type old_type, bool check_type);
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extern void e820__print_table(char *who);
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extern int e820__update_table(struct e820_table *table);
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extern void e820__update_table_print(void);
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extern unsigned long e820__end_of_ram_pfn(void);
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extern unsigned long e820__end_of_low_ram_pfn(void);
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extern u64 e820__memblock_alloc_reserved(u64 size, u64 align);
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extern void e820__memblock_setup(void);
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extern void e820__reserve_setup_data(void);
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extern void e820__finish_early_params(void);
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extern void e820__reserve_resources(void);
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extern void e820__reserve_resources_late(void);
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extern void e820__memory_setup(void);
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extern void e820__memory_setup_extended(u64 phys_addr, u32 data_len);
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extern char *e820__memory_setup_default(void);
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extern void e820__setup_pci_gap(void);
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extern void e820__reallocate_tables(void);
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extern void e820__register_nosave_regions(unsigned long limit_pfn);
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extern int e820__get_entry_type(u64 start, u64 end);
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/*
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* Returns true iff the specified range [start,end) is completely contained inside
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* the ISA region.
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*/
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static inline bool is_ISA_range(u64 start, u64 end)
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{
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return start >= ISA_START_ADDRESS && end <= ISA_END_ADDRESS;
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}
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#endif /* _ASM_E820_API_H */
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