c912f19ee3
This patch removes the hard coded assumption that the TX ring uses hardware FIFO 1. This allows the hardware FIFO 1 to be used for RX and the next free FIFO for TX. This gives the opportunity to minimize the number of SPI transfers in the IRQ handler. The read of the IRQ status register and RX FIFO status registers can be combined into single SPI transfer. If the RX ring uses FIFO 1, the overall length of the transfer is smaller than in the original layout, where the RX FIFO comes after the TX FIFO. Link: https://lore.kernel.org/all/20220217103826.2299157-2-mkl@pengutronix.de Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
119 lines
3.1 KiB
C
119 lines
3.1 KiB
C
// SPDX-License-Identifier: GPL-2.0
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//
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// mcp251xfd - Microchip MCP251xFD Family CAN controller driver
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//
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// Copyright (c) 2019, 2020, 2021 Pengutronix,
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// Marc Kleine-Budde <kernel@pengutronix.de>
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//
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// Based on:
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//
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// CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface
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//
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// Copyright (c) 2019 Martin Sperl <kernel@martin.sperl.org>
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//
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#include <linux/bitfield.h>
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#include "mcp251xfd.h"
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static int
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mcp251xfd_chip_rx_fifo_init_one(const struct mcp251xfd_priv *priv,
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const struct mcp251xfd_rx_ring *ring)
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{
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u32 fifo_con;
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/* Enable RXOVIE on _all_ RX FIFOs, not just the last one.
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*
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* FIFOs hit by a RX MAB overflow and RXOVIE enabled will
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* generate a RXOVIF, use this to properly detect RX MAB
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* overflows.
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*/
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fifo_con = FIELD_PREP(MCP251XFD_REG_FIFOCON_FSIZE_MASK,
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ring->obj_num - 1) |
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MCP251XFD_REG_FIFOCON_RXTSEN |
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MCP251XFD_REG_FIFOCON_RXOVIE |
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MCP251XFD_REG_FIFOCON_TFNRFNIE;
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if (mcp251xfd_is_fd_mode(priv))
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fifo_con |= FIELD_PREP(MCP251XFD_REG_FIFOCON_PLSIZE_MASK,
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MCP251XFD_REG_FIFOCON_PLSIZE_64);
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else
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fifo_con |= FIELD_PREP(MCP251XFD_REG_FIFOCON_PLSIZE_MASK,
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MCP251XFD_REG_FIFOCON_PLSIZE_8);
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return regmap_write(priv->map_reg,
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MCP251XFD_REG_FIFOCON(ring->fifo_nr), fifo_con);
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}
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static int
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mcp251xfd_chip_rx_filter_init_one(const struct mcp251xfd_priv *priv,
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const struct mcp251xfd_rx_ring *ring)
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{
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u32 fltcon;
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fltcon = MCP251XFD_REG_FLTCON_FLTEN(ring->nr) |
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MCP251XFD_REG_FLTCON_FBP(ring->nr, ring->fifo_nr);
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return regmap_update_bits(priv->map_reg,
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MCP251XFD_REG_FLTCON(ring->nr >> 2),
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MCP251XFD_REG_FLTCON_FLT_MASK(ring->nr),
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fltcon);
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}
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int mcp251xfd_chip_fifo_init(const struct mcp251xfd_priv *priv)
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{
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const struct mcp251xfd_tx_ring *tx_ring = priv->tx;
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const struct mcp251xfd_rx_ring *rx_ring;
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u32 val;
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int err, n;
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/* TEF */
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val = FIELD_PREP(MCP251XFD_REG_TEFCON_FSIZE_MASK,
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tx_ring->obj_num - 1) |
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MCP251XFD_REG_TEFCON_TEFTSEN |
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MCP251XFD_REG_TEFCON_TEFOVIE |
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MCP251XFD_REG_TEFCON_TEFNEIE;
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err = regmap_write(priv->map_reg, MCP251XFD_REG_TEFCON, val);
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if (err)
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return err;
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/* TX FIFO */
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val = FIELD_PREP(MCP251XFD_REG_FIFOCON_FSIZE_MASK,
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tx_ring->obj_num - 1) |
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MCP251XFD_REG_FIFOCON_TXEN |
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MCP251XFD_REG_FIFOCON_TXATIE;
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if (mcp251xfd_is_fd_mode(priv))
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val |= FIELD_PREP(MCP251XFD_REG_FIFOCON_PLSIZE_MASK,
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MCP251XFD_REG_FIFOCON_PLSIZE_64);
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else
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val |= FIELD_PREP(MCP251XFD_REG_FIFOCON_PLSIZE_MASK,
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MCP251XFD_REG_FIFOCON_PLSIZE_8);
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if (priv->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT)
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val |= FIELD_PREP(MCP251XFD_REG_FIFOCON_TXAT_MASK,
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MCP251XFD_REG_FIFOCON_TXAT_ONE_SHOT);
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else
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val |= FIELD_PREP(MCP251XFD_REG_FIFOCON_TXAT_MASK,
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MCP251XFD_REG_FIFOCON_TXAT_UNLIMITED);
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err = regmap_write(priv->map_reg,
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MCP251XFD_REG_FIFOCON(priv->tx->fifo_nr),
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val);
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if (err)
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return err;
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/* RX FIFOs */
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mcp251xfd_for_each_rx_ring(priv, rx_ring, n) {
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err = mcp251xfd_chip_rx_fifo_init_one(priv, rx_ring);
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if (err)
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return err;
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err = mcp251xfd_chip_rx_filter_init_one(priv, rx_ring);
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if (err)
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return err;
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}
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return 0;
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}
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