74c1b2338e
The cn10k hardware ptp timestamp format has been modified primarily to support 1-step ptp clock. The 64-bit timestamp used by hardware is split into two 32-bit fields, the upper one holds seconds, the lower one nanoseconds. A new register (PTP_CLOCK_SEC) has been added that returns the current seconds value. The nanoseconds register PTP_CLOCK_HI resets after every second. The cn10k RPM block provides Rx/Tx timestamps to the NIX block using the new timestamp format. The software can read the current timestamp in nanoseconds by reading both PTP_CLOCK_SEC & PTP_CLOCK_HI registers. This patch provides support for new timestamp format. Signed-off-by: Naveen Mamindlapalli <naveenm@marvell.com> Signed-off-by: Sunil Kovvuri Goutham <sgoutham@marvell.com> Signed-off-by: Rakesh Babu Saladi <rsaladi2@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
29 lines
550 B
C
29 lines
550 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Marvell PTP driver
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*
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* Copyright (C) 2020 Marvell.
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*
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*/
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#ifndef PTP_H
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#define PTP_H
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#include <linux/timecounter.h>
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#include <linux/time64.h>
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#include <linux/spinlock.h>
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struct ptp {
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struct pci_dev *pdev;
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void __iomem *reg_base;
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u64 (*read_ptp_tstmp)(struct ptp *ptp);
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spinlock_t ptp_lock; /* lock */
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u32 clock_rate;
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};
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struct ptp *ptp_get(void);
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void ptp_put(struct ptp *ptp);
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void ptp_start(struct ptp *ptp, u64 sclk, u32 ext_clk_freq, u32 extts);
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extern struct pci_driver ptp_driver;
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#endif
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