867f4eeee8
Commit56c8ccf331("ath11k: Add register access logic for WCN6750") regressed QCN9074. With the above mentioned commit, writes are failing for some registers on QCN9074 although the device seems to work normally. ath11k_pci 0000:03:00.0: failed to set pcie link register0x01e0e0a8: 0xffffffff != 0x00000010 ath11k_pci 0000:03:00.0: failed to set sysclk: -110 PCIe devices in ath11k (QCA6390, WCN6855, QCN9074, WCN6750) use window concept for register accesses. There are two schemes, dynamic & static window. In dynamic window scheme, a single window(region in the BAR) is mapped either to CE or DP register windows at any give time. QCA6390 & WCN6855 follow this scheme for register accesses. In static window scheme, CE & DP register windows are statically mapped to separate regions with in the BAR so that there is no switching of register windows between CE & DP register accesses. QCN9074 & WCN6750 follow this scheme although the window start offsets are different for QCN9074 & WCN6750. QCN9074 uses 3rd & 2nd window for DP & CE register accesses respectively whereas WCN6750 uses 1st & 2nd window for DP & CE. In QCN9074, along with 2nd & 3rd windows, 1st window is also used for certain configurations which commit56c8ccf331("ath11k: Add register access logic for WCN6750") did not account for and hence the regression. Fix this by going back to the original way of accessing the registers on QCN9074. Since this diverges from WCN6750 way of accessing registers, it is required to register window_read32/window_write32() pci_ops for WCN6750. We can also get rid of dp_window_idx & ce_window_idx members in hw_params, so remove them. Also add a new API ath11k_pcic_register_pci_ops() for registering pci_ops to the ath11k core. This API checks for mandatory pci_ops() and reports error if those are missing. Also initialize unused pci_ops to NULL. Tested-on: WCN6750 hw1.0 AHB WLAN.MSL.1.0.1-00887-QCAMSLSWPLZ-1 Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.6.0.1-00861-QCAHKSWPL_SILICONZ-1 Fixes:56c8ccf331("ath11k: Add register access logic for WCN6750") Reported-by: Maxime Bizon <mbizon@freebox.fr> Tested-by: Maxime Bizon <mbizon@freebox.fr> Signed-off-by: Manikanta Pubbisetty <quic_mpubbise@quicinc.com> Signed-off-by: Kalle Valo <quic_kvalo@quicinc.com> Link: https://lore.kernel.org/r/20220608062954.27792-1-quic_mpubbise@quicinc.com
48 lines
1.9 KiB
C
48 lines
1.9 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause-Clear */
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/*
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* Copyright (c) 2019-2021 The Linux Foundation. All rights reserved.
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* Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef _ATH11K_PCI_CMN_H
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#define _ATH11K_PCI_CMN_H
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#include "core.h"
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#define ATH11K_PCI_IRQ_CE0_OFFSET 3
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#define ATH11K_PCI_IRQ_DP_OFFSET 14
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#define ATH11K_PCI_WINDOW_ENABLE_BIT 0x40000000
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#define ATH11K_PCI_WINDOW_REG_ADDRESS 0x310c
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#define ATH11K_PCI_WINDOW_VALUE_MASK GENMASK(24, 19)
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#define ATH11K_PCI_WINDOW_START 0x80000
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#define ATH11K_PCI_WINDOW_RANGE_MASK GENMASK(18, 0)
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/* BAR0 + 4k is always accessible, and no
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* need to force wakeup.
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* 4K - 32 = 0xFE0
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*/
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#define ATH11K_PCI_ACCESS_ALWAYS_OFF 0xFE0
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int ath11k_pcic_get_user_msi_assignment(struct ath11k_base *ab, char *user_name,
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int *num_vectors, u32 *user_base_data,
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u32 *base_vector);
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void ath11k_pcic_write32(struct ath11k_base *ab, u32 offset, u32 value);
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u32 ath11k_pcic_read32(struct ath11k_base *ab, u32 offset);
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void ath11k_pcic_get_msi_address(struct ath11k_base *ab, u32 *msi_addr_lo,
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u32 *msi_addr_hi);
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void ath11k_pcic_get_ce_msi_idx(struct ath11k_base *ab, u32 ce_id, u32 *msi_idx);
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void ath11k_pcic_free_irq(struct ath11k_base *ab);
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int ath11k_pcic_config_irq(struct ath11k_base *ab);
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void ath11k_pcic_ext_irq_enable(struct ath11k_base *ab);
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void ath11k_pcic_ext_irq_disable(struct ath11k_base *ab);
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void ath11k_pcic_stop(struct ath11k_base *ab);
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int ath11k_pcic_start(struct ath11k_base *ab);
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int ath11k_pcic_map_service_to_pipe(struct ath11k_base *ab, u16 service_id,
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u8 *ul_pipe, u8 *dl_pipe);
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void ath11k_pcic_ce_irqs_enable(struct ath11k_base *ab);
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void ath11k_pcic_ce_irq_disable_sync(struct ath11k_base *ab);
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int ath11k_pcic_init_msi_config(struct ath11k_base *ab);
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int ath11k_pcic_register_pci_ops(struct ath11k_base *ab,
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const struct ath11k_pci_ops *pci_ops);
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#endif
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