fb91526b5f
To support reset of infra_ao, add the index of infra_ao reset of thermal/svs/pcei for MT8192 and thermal/svs for MT8195. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> [Nícolas: Test for MT8192] Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20220523093346.28493-14-rex-bc.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
35 lines
1.3 KiB
C
35 lines
1.3 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)*/
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/*
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* Copyright (c) 2021 MediaTek Inc.
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* Author: Christine Zhu <christine.zhu@mediatek.com>
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*/
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#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8195
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#define _DT_BINDINGS_RESET_CONTROLLER_MT8195
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/* TOPRGU resets */
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#define MT8195_TOPRGU_CONN_MCU_SW_RST 0
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#define MT8195_TOPRGU_INFRA_GRST_SW_RST 1
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#define MT8195_TOPRGU_APU_SW_RST 2
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#define MT8195_TOPRGU_INFRA_AO_GRST_SW_RST 6
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#define MT8195_TOPRGU_MMSYS_SW_RST 7
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#define MT8195_TOPRGU_MFG_SW_RST 8
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#define MT8195_TOPRGU_VENC_SW_RST 9
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#define MT8195_TOPRGU_VDEC_SW_RST 10
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#define MT8195_TOPRGU_IMG_SW_RST 11
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#define MT8195_TOPRGU_APMIXEDSYS_SW_RST 13
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#define MT8195_TOPRGU_AUDIO_SW_RST 14
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#define MT8195_TOPRGU_CAMSYS_SW_RST 15
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#define MT8195_TOPRGU_EDPTX_SW_RST 16
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#define MT8195_TOPRGU_ADSPSYS_SW_RST 21
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#define MT8195_TOPRGU_DPTX_SW_RST 22
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#define MT8195_TOPRGU_SPMI_MST_SW_RST 23
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#define MT8195_TOPRGU_SW_RST_NUM 16
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/* INFRA resets */
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#define MT8195_INFRA_RST0_THERM_CTRL_SWRST 0
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#define MT8195_INFRA_RST3_THERM_CTRL_PTP_SWRST 1
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#define MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST 2
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#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8195 */
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