63a6ef2360
Add clock, memory controller, powergate and reset dt-binding headers for Host1x and VIC on Tegra234. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
73 lines
2.5 KiB
C
73 lines
2.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */
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#ifndef DT_BINDINGS_RESET_TEGRA234_RESET_H
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#define DT_BINDINGS_RESET_TEGRA234_RESET_H
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/**
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* @file
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* @defgroup bpmp_reset_ids Reset ID's
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* @brief Identifiers for Resets controllable by firmware
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* @{
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*/
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#define TEGRA234_RESET_PEX1_CORE_6 11U
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#define TEGRA234_RESET_PEX1_CORE_6_APB 12U
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#define TEGRA234_RESET_PEX1_COMMON_APB 13U
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#define TEGRA234_RESET_PEX2_CORE_7 14U
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#define TEGRA234_RESET_PEX2_CORE_7_APB 15U
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#define TEGRA234_RESET_GPCDMA 18U
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#define TEGRA234_RESET_HDA 20U
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#define TEGRA234_RESET_HDACODEC 21U
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#define TEGRA234_RESET_I2C1 24U
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#define TEGRA234_RESET_PEX2_CORE_8 25U
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#define TEGRA234_RESET_PEX2_CORE_8_APB 26U
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#define TEGRA234_RESET_PEX2_CORE_9 27U
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#define TEGRA234_RESET_PEX2_CORE_9_APB 28U
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#define TEGRA234_RESET_I2C2 29U
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#define TEGRA234_RESET_I2C3 30U
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#define TEGRA234_RESET_I2C4 31U
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#define TEGRA234_RESET_I2C6 32U
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#define TEGRA234_RESET_I2C7 33U
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#define TEGRA234_RESET_I2C8 34U
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#define TEGRA234_RESET_I2C9 35U
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#define TEGRA234_RESET_MGBE0_PCS 45U
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#define TEGRA234_RESET_MGBE0_MAC 46U
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#define TEGRA234_RESET_MGBE1_PCS 49U
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#define TEGRA234_RESET_MGBE1_MAC 50U
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#define TEGRA234_RESET_MGBE2_PCS 53U
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#define TEGRA234_RESET_MGBE2_MAC 54U
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#define TEGRA234_RESET_PEX2_CORE_10 56U
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#define TEGRA234_RESET_PEX2_CORE_10_APB 57U
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#define TEGRA234_RESET_PEX2_COMMON_APB 58U
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#define TEGRA234_RESET_PWM1 68U
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#define TEGRA234_RESET_PWM2 69U
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#define TEGRA234_RESET_PWM3 70U
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#define TEGRA234_RESET_PWM4 71U
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#define TEGRA234_RESET_PWM5 72U
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#define TEGRA234_RESET_PWM6 73U
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#define TEGRA234_RESET_PWM7 74U
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#define TEGRA234_RESET_PWM8 75U
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#define TEGRA234_RESET_QSPI0 76U
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#define TEGRA234_RESET_QSPI1 77U
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#define TEGRA234_RESET_SDMMC4 85U
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#define TEGRA234_RESET_MGBE3_PCS 87U
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#define TEGRA234_RESET_MGBE3_MAC 88U
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#define TEGRA234_RESET_UARTA 100U
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#define TEGRA234_RESET_VIC 113U
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#define TEGRA234_RESET_PEX0_CORE_0 116U
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#define TEGRA234_RESET_PEX0_CORE_1 117U
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#define TEGRA234_RESET_PEX0_CORE_2 118U
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#define TEGRA234_RESET_PEX0_CORE_3 119U
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#define TEGRA234_RESET_PEX0_CORE_4 120U
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#define TEGRA234_RESET_PEX0_CORE_0_APB 121U
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#define TEGRA234_RESET_PEX0_CORE_1_APB 122U
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#define TEGRA234_RESET_PEX0_CORE_2_APB 123U
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#define TEGRA234_RESET_PEX0_CORE_3_APB 124U
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#define TEGRA234_RESET_PEX0_CORE_4_APB 125U
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#define TEGRA234_RESET_PEX0_COMMON_APB 126U
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#define TEGRA234_RESET_PEX1_CORE_5 129U
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#define TEGRA234_RESET_PEX1_CORE_5_APB 130U
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/** @} */
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#endif
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