01d5e7872c
- Cleanups and generalzation of code shared by SEV and TDX
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Merge tag 'x86_sev_for_v5.17_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 SEV updates from Borislav Petkov:
"The accumulated pile of x86/sev generalizations and cleanups:
- Share the SEV string unrolling logic with TDX as TDX guests need it
too
- Cleanups and generalzation of code shared by SEV and TDX"
* tag 'x86_sev_for_v5.17_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
x86/sev: Move common memory encryption code to mem_encrypt.c
x86/sev: Rename mem_encrypt.c to mem_encrypt_amd.c
x86/sev: Use CC_ATTR attribute to generalize string I/O unroll
x86/sev: Remove do_early_exception() forward declarations
x86/head64: Carve out the guest encryption postprocessing into a helper
x86/sev: Get rid of excessive use of defines
x86/sev: Shorten GHCB terminate macro names
92 lines
2.7 KiB
C
92 lines
2.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* AMD SEV header common between the guest and the hypervisor.
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*
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* Author: Brijesh Singh <brijesh.singh@amd.com>
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*/
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#ifndef __ASM_X86_SEV_COMMON_H
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#define __ASM_X86_SEV_COMMON_H
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#define GHCB_MSR_INFO_POS 0
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#define GHCB_DATA_LOW 12
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#define GHCB_MSR_INFO_MASK (BIT_ULL(GHCB_DATA_LOW) - 1)
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#define GHCB_DATA(v) \
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(((unsigned long)(v) & ~GHCB_MSR_INFO_MASK) >> GHCB_DATA_LOW)
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/* SEV Information Request/Response */
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#define GHCB_MSR_SEV_INFO_RESP 0x001
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#define GHCB_MSR_SEV_INFO_REQ 0x002
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#define GHCB_MSR_SEV_INFO(_max, _min, _cbit) \
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/* GHCBData[63:48] */ \
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((((_max) & 0xffff) << 48) | \
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/* GHCBData[47:32] */ \
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(((_min) & 0xffff) << 32) | \
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/* GHCBData[31:24] */ \
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(((_cbit) & 0xff) << 24) | \
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GHCB_MSR_SEV_INFO_RESP)
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#define GHCB_MSR_INFO(v) ((v) & 0xfffUL)
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#define GHCB_MSR_PROTO_MAX(v) (((v) >> 48) & 0xffff)
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#define GHCB_MSR_PROTO_MIN(v) (((v) >> 32) & 0xffff)
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/* CPUID Request/Response */
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#define GHCB_MSR_CPUID_REQ 0x004
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#define GHCB_MSR_CPUID_RESP 0x005
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#define GHCB_MSR_CPUID_FUNC_POS 32
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#define GHCB_MSR_CPUID_FUNC_MASK 0xffffffff
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#define GHCB_MSR_CPUID_VALUE_POS 32
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#define GHCB_MSR_CPUID_VALUE_MASK 0xffffffff
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#define GHCB_MSR_CPUID_REG_POS 30
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#define GHCB_MSR_CPUID_REG_MASK 0x3
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#define GHCB_CPUID_REQ_EAX 0
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#define GHCB_CPUID_REQ_EBX 1
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#define GHCB_CPUID_REQ_ECX 2
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#define GHCB_CPUID_REQ_EDX 3
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#define GHCB_CPUID_REQ(fn, reg) \
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/* GHCBData[11:0] */ \
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(GHCB_MSR_CPUID_REQ | \
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/* GHCBData[31:12] */ \
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(((unsigned long)(reg) & 0x3) << 30) | \
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/* GHCBData[63:32] */ \
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(((unsigned long)fn) << 32))
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/* AP Reset Hold */
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#define GHCB_MSR_AP_RESET_HOLD_REQ 0x006
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#define GHCB_MSR_AP_RESET_HOLD_RESP 0x007
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/* GHCB Hypervisor Feature Request/Response */
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#define GHCB_MSR_HV_FT_REQ 0x080
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#define GHCB_MSR_HV_FT_RESP 0x081
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#define GHCB_MSR_TERM_REQ 0x100
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#define GHCB_MSR_TERM_REASON_SET_POS 12
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#define GHCB_MSR_TERM_REASON_SET_MASK 0xf
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#define GHCB_MSR_TERM_REASON_POS 16
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#define GHCB_MSR_TERM_REASON_MASK 0xff
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#define GHCB_SEV_TERM_REASON(reason_set, reason_val) \
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/* GHCBData[15:12] */ \
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(((((u64)reason_set) & 0xf) << 12) | \
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/* GHCBData[23:16] */ \
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((((u64)reason_val) & 0xff) << 16))
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#define GHCB_SEV_ES_GEN_REQ 0
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#define GHCB_SEV_ES_PROT_UNSUPPORTED 1
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#define GHCB_RESP_CODE(v) ((v) & GHCB_MSR_INFO_MASK)
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/*
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* Error codes related to GHCB input that can be communicated back to the guest
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* by setting the lower 32-bits of the GHCB SW_EXITINFO1 field to 2.
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*/
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#define GHCB_ERR_NOT_REGISTERED 1
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#define GHCB_ERR_INVALID_USAGE 2
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#define GHCB_ERR_INVALID_SCRATCH_AREA 3
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#define GHCB_ERR_MISSING_INPUT 4
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#define GHCB_ERR_INVALID_INPUT 5
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#define GHCB_ERR_INVALID_EVENT 6
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#endif
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