642a7d49c2
The logic that detects, enables and disables pfvf interrupts was
expecting a single CSR per VF. Instead, the source and mask register are
two registers with a bit per VF.
Due to this, the driver is reading and setting reserved CSRs and not
masking the correct source of interrupts.
Fix the access to the source and mask register for QAT GEN4 devices by
removing the outer loop in adf_gen4_get_vf2pf_sources(),
adf_gen4_enable_vf2pf_interrupts() and
adf_gen4_disable_vf2pf_interrupts() and changing the helper macros
ADF_4XXX_VM2PF_SOU and ADF_4XXX_VM2PF_MSK.
Fixes: a9dc0d9666 ("crypto: qat - add PFVF support to the GEN4 host driver")
Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
Co-developed-by: Siming Wan <siming.wan@intel.com>
Signed-off-by: Siming Wan <siming.wan@intel.com>
Reviewed-by: Xin Zeng <xin.zeng@intel.com>
Reviewed-by: Wojciech Ziemba <wojciech.ziemba@intel.com>
Reviewed-by: Marco Chiappero <marco.chiappero@intel.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
124 lines
3.6 KiB
C
124 lines
3.6 KiB
C
// SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only)
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/* Copyright(c) 2021 Intel Corporation */
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#include <linux/iopoll.h>
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#include <linux/mutex.h>
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#include <linux/types.h>
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#include "adf_accel_devices.h"
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#include "adf_common_drv.h"
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#include "adf_gen4_pfvf.h"
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#include "adf_pfvf_pf_proto.h"
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#include "adf_pfvf_utils.h"
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#define ADF_4XXX_PF2VM_OFFSET(i) (0x40B010 + ((i) * 0x20))
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#define ADF_4XXX_VM2PF_OFFSET(i) (0x40B014 + ((i) * 0x20))
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/* VF2PF interrupt source registers */
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#define ADF_4XXX_VM2PF_SOU 0x41A180
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#define ADF_4XXX_VM2PF_MSK 0x41A1C0
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#define ADF_PFVF_GEN4_MSGTYPE_SHIFT 2
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#define ADF_PFVF_GEN4_MSGTYPE_MASK 0x3F
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#define ADF_PFVF_GEN4_MSGDATA_SHIFT 8
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#define ADF_PFVF_GEN4_MSGDATA_MASK 0xFFFFFF
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static const struct pfvf_csr_format csr_gen4_fmt = {
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{ ADF_PFVF_GEN4_MSGTYPE_SHIFT, ADF_PFVF_GEN4_MSGTYPE_MASK },
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{ ADF_PFVF_GEN4_MSGDATA_SHIFT, ADF_PFVF_GEN4_MSGDATA_MASK },
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};
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static u32 adf_gen4_pf_get_pf2vf_offset(u32 i)
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{
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return ADF_4XXX_PF2VM_OFFSET(i);
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}
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static u32 adf_gen4_pf_get_vf2pf_offset(u32 i)
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{
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return ADF_4XXX_VM2PF_OFFSET(i);
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}
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static u32 adf_gen4_get_vf2pf_sources(void __iomem *pmisc_addr)
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{
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u32 sou, mask;
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sou = ADF_CSR_RD(pmisc_addr, ADF_4XXX_VM2PF_SOU);
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mask = ADF_CSR_RD(pmisc_addr, ADF_4XXX_VM2PF_MSK);
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return sou &= ~mask;
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}
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static void adf_gen4_enable_vf2pf_interrupts(void __iomem *pmisc_addr,
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u32 vf_mask)
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{
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unsigned int val;
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val = ADF_CSR_RD(pmisc_addr, ADF_4XXX_VM2PF_MSK) & ~vf_mask;
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ADF_CSR_WR(pmisc_addr, ADF_4XXX_VM2PF_MSK, val);
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}
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static void adf_gen4_disable_vf2pf_interrupts(void __iomem *pmisc_addr,
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u32 vf_mask)
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{
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unsigned int val;
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val = ADF_CSR_RD(pmisc_addr, ADF_4XXX_VM2PF_MSK) | vf_mask;
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ADF_CSR_WR(pmisc_addr, ADF_4XXX_VM2PF_MSK, val);
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}
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static int adf_gen4_pfvf_send(struct adf_accel_dev *accel_dev,
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struct pfvf_message msg, u32 pfvf_offset,
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struct mutex *csr_lock)
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{
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void __iomem *pmisc_addr = adf_get_pmisc_base(accel_dev);
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u32 csr_val;
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int ret;
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csr_val = adf_pfvf_csr_msg_of(accel_dev, msg, &csr_gen4_fmt);
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if (unlikely(!csr_val))
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return -EINVAL;
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mutex_lock(csr_lock);
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ADF_CSR_WR(pmisc_addr, pfvf_offset, csr_val | ADF_PFVF_INT);
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/* Wait for confirmation from remote that it received the message */
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ret = read_poll_timeout(ADF_CSR_RD, csr_val, !(csr_val & ADF_PFVF_INT),
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ADF_PFVF_MSG_ACK_DELAY_US,
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ADF_PFVF_MSG_ACK_MAX_DELAY_US,
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true, pmisc_addr, pfvf_offset);
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if (ret < 0)
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dev_dbg(&GET_DEV(accel_dev), "ACK not received from remote\n");
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mutex_unlock(csr_lock);
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return ret;
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}
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static struct pfvf_message adf_gen4_pfvf_recv(struct adf_accel_dev *accel_dev,
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u32 pfvf_offset, u8 compat_ver)
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{
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void __iomem *pmisc_addr = adf_get_pmisc_base(accel_dev);
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u32 csr_val;
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/* Read message from the CSR */
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csr_val = ADF_CSR_RD(pmisc_addr, pfvf_offset);
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/* We can now acknowledge the message reception by clearing the
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* interrupt bit
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*/
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ADF_CSR_WR(pmisc_addr, pfvf_offset, csr_val & ~ADF_PFVF_INT);
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/* Return the pfvf_message format */
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return adf_pfvf_message_of(accel_dev, csr_val, &csr_gen4_fmt);
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}
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void adf_gen4_init_pf_pfvf_ops(struct adf_pfvf_ops *pfvf_ops)
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{
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pfvf_ops->enable_comms = adf_enable_pf2vf_comms;
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pfvf_ops->get_pf2vf_offset = adf_gen4_pf_get_pf2vf_offset;
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pfvf_ops->get_vf2pf_offset = adf_gen4_pf_get_vf2pf_offset;
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pfvf_ops->get_vf2pf_sources = adf_gen4_get_vf2pf_sources;
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pfvf_ops->enable_vf2pf_interrupts = adf_gen4_enable_vf2pf_interrupts;
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pfvf_ops->disable_vf2pf_interrupts = adf_gen4_disable_vf2pf_interrupts;
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pfvf_ops->send_msg = adf_gen4_pfvf_send;
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pfvf_ops->recv_msg = adf_gen4_pfvf_recv;
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}
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EXPORT_SYMBOL_GPL(adf_gen4_init_pf_pfvf_ops);
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