2685c77b80
The existing mail mechanism only supports writing of workload types.
However, mailbox command for RFIM (cmd = 0x08) also requires write
operation which is ignored. This results in failing to store RFI
restriction.
Fixint this requires enhancing mailbox writes for non workload
commands too, so remove the check for MBOX_CMD_WORKLOAD_TYPE_WRITE
in mailbox write to allow this other write commands to be supoorted.
At the same time, however, we have to make sure that there is no
impact on read commands, by avoiding to write anything into the
mailbox data register.
To properly implement that, add two separate functions for mbox read
and write commands for the processor thermal workload command type.
This helps to distinguish the read and write workload command types
from each other while sending mbox commands.
Fixes: 5d6fbc96bd ("thermal/drivers/int340x: processor_thermal: Export additional attributes")
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Cc: 5.14+ <stable@vger.kernel.org> # 5.14+
Acked-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
[ rjw: Changelog edits ]
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
300 lines
8.1 KiB
C
300 lines
8.1 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* processor thermal device RFIM control
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* Copyright (c) 2020, Intel Corporation.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include "processor_thermal_device.h"
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MODULE_IMPORT_NS(INT340X_THERMAL);
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struct mmio_reg {
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int read_only;
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u32 offset;
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int bits;
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u16 mask;
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u16 shift;
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};
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/* These will represent sysfs attribute names */
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static const char * const fivr_strings[] = {
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"vco_ref_code_lo",
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"vco_ref_code_hi",
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"spread_spectrum_pct",
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"spread_spectrum_clk_enable",
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"rfi_vco_ref_code",
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"fivr_fffc_rev",
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NULL
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};
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static const struct mmio_reg tgl_fivr_mmio_regs[] = {
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{ 0, 0x5A18, 3, 0x7, 11}, /* vco_ref_code_lo */
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{ 0, 0x5A18, 8, 0xFF, 16}, /* vco_ref_code_hi */
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{ 0, 0x5A08, 8, 0xFF, 0}, /* spread_spectrum_pct */
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{ 0, 0x5A08, 1, 0x1, 8}, /* spread_spectrum_clk_enable */
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{ 1, 0x5A10, 12, 0xFFF, 0}, /* rfi_vco_ref_code */
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{ 1, 0x5A14, 2, 0x3, 1}, /* fivr_fffc_rev */
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};
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/* These will represent sysfs attribute names */
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static const char * const dvfs_strings[] = {
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"rfi_restriction_run_busy",
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"rfi_restriction_err_code",
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"rfi_restriction_data_rate",
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"rfi_restriction_data_rate_base",
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"ddr_data_rate_point_0",
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"ddr_data_rate_point_1",
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"ddr_data_rate_point_2",
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"ddr_data_rate_point_3",
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"rfi_disable",
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NULL
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};
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static const struct mmio_reg adl_dvfs_mmio_regs[] = {
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{ 0, 0x5A38, 1, 0x1, 31}, /* rfi_restriction_run_busy */
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{ 0, 0x5A38, 7, 0x7F, 24}, /* rfi_restriction_err_code */
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{ 0, 0x5A38, 8, 0xFF, 16}, /* rfi_restriction_data_rate */
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{ 0, 0x5A38, 16, 0xFFFF, 0}, /* rfi_restriction_data_rate_base */
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{ 0, 0x5A30, 10, 0x3FF, 0}, /* ddr_data_rate_point_0 */
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{ 0, 0x5A30, 10, 0x3FF, 10}, /* ddr_data_rate_point_1 */
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{ 0, 0x5A30, 10, 0x3FF, 20}, /* ddr_data_rate_point_2 */
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{ 0, 0x5A30, 10, 0x3FF, 30}, /* ddr_data_rate_point_3 */
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{ 0, 0x5A40, 1, 0x1, 0}, /* rfi_disable */
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};
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#define RFIM_SHOW(suffix, table)\
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static ssize_t suffix##_show(struct device *dev,\
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struct device_attribute *attr,\
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char *buf)\
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{\
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struct proc_thermal_device *proc_priv;\
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struct pci_dev *pdev = to_pci_dev(dev);\
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const struct mmio_reg *mmio_regs;\
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const char **match_strs;\
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u32 reg_val;\
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int ret;\
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\
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proc_priv = pci_get_drvdata(pdev);\
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if (table) {\
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match_strs = (const char **)dvfs_strings;\
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mmio_regs = adl_dvfs_mmio_regs;\
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} else { \
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match_strs = (const char **)fivr_strings;\
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mmio_regs = tgl_fivr_mmio_regs;\
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} \
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\
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ret = match_string(match_strs, -1, attr->attr.name);\
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if (ret < 0)\
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return ret;\
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reg_val = readl((void __iomem *) (proc_priv->mmio_base + mmio_regs[ret].offset));\
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ret = (reg_val >> mmio_regs[ret].shift) & mmio_regs[ret].mask;\
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return sprintf(buf, "%u\n", ret);\
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}
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#define RFIM_STORE(suffix, table)\
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static ssize_t suffix##_store(struct device *dev,\
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struct device_attribute *attr,\
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const char *buf, size_t count)\
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{\
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struct proc_thermal_device *proc_priv;\
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struct pci_dev *pdev = to_pci_dev(dev);\
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unsigned int input;\
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const char **match_strs;\
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const struct mmio_reg *mmio_regs;\
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int ret, err;\
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u32 reg_val;\
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u32 mask;\
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\
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proc_priv = pci_get_drvdata(pdev);\
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if (table) {\
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match_strs = (const char **)dvfs_strings;\
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mmio_regs = adl_dvfs_mmio_regs;\
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} else { \
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match_strs = (const char **)fivr_strings;\
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mmio_regs = tgl_fivr_mmio_regs;\
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} \
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\
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ret = match_string(match_strs, -1, attr->attr.name);\
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if (ret < 0)\
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return ret;\
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if (mmio_regs[ret].read_only)\
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return -EPERM;\
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err = kstrtouint(buf, 10, &input);\
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if (err)\
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return err;\
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mask = GENMASK(mmio_regs[ret].shift + mmio_regs[ret].bits - 1, mmio_regs[ret].shift);\
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reg_val = readl((void __iomem *) (proc_priv->mmio_base + mmio_regs[ret].offset));\
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reg_val &= ~mask;\
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reg_val |= (input << mmio_regs[ret].shift);\
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writel(reg_val, (void __iomem *) (proc_priv->mmio_base + mmio_regs[ret].offset));\
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return count;\
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}
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RFIM_SHOW(vco_ref_code_lo, 0)
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RFIM_SHOW(vco_ref_code_hi, 0)
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RFIM_SHOW(spread_spectrum_pct, 0)
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RFIM_SHOW(spread_spectrum_clk_enable, 0)
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RFIM_SHOW(rfi_vco_ref_code, 0)
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RFIM_SHOW(fivr_fffc_rev, 0)
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RFIM_STORE(vco_ref_code_lo, 0)
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RFIM_STORE(vco_ref_code_hi, 0)
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RFIM_STORE(spread_spectrum_pct, 0)
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RFIM_STORE(spread_spectrum_clk_enable, 0)
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RFIM_STORE(rfi_vco_ref_code, 0)
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RFIM_STORE(fivr_fffc_rev, 0)
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static DEVICE_ATTR_RW(vco_ref_code_lo);
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static DEVICE_ATTR_RW(vco_ref_code_hi);
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static DEVICE_ATTR_RW(spread_spectrum_pct);
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static DEVICE_ATTR_RW(spread_spectrum_clk_enable);
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static DEVICE_ATTR_RW(rfi_vco_ref_code);
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static DEVICE_ATTR_RW(fivr_fffc_rev);
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static struct attribute *fivr_attrs[] = {
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&dev_attr_vco_ref_code_lo.attr,
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&dev_attr_vco_ref_code_hi.attr,
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&dev_attr_spread_spectrum_pct.attr,
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&dev_attr_spread_spectrum_clk_enable.attr,
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&dev_attr_rfi_vco_ref_code.attr,
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&dev_attr_fivr_fffc_rev.attr,
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NULL
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};
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static const struct attribute_group fivr_attribute_group = {
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.attrs = fivr_attrs,
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.name = "fivr"
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};
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RFIM_SHOW(rfi_restriction_run_busy, 1)
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RFIM_SHOW(rfi_restriction_err_code, 1)
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RFIM_SHOW(rfi_restriction_data_rate, 1)
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RFIM_SHOW(ddr_data_rate_point_0, 1)
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RFIM_SHOW(ddr_data_rate_point_1, 1)
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RFIM_SHOW(ddr_data_rate_point_2, 1)
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RFIM_SHOW(ddr_data_rate_point_3, 1)
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RFIM_SHOW(rfi_disable, 1)
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RFIM_STORE(rfi_restriction_run_busy, 1)
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RFIM_STORE(rfi_restriction_err_code, 1)
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RFIM_STORE(rfi_restriction_data_rate, 1)
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RFIM_STORE(rfi_disable, 1)
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static DEVICE_ATTR_RW(rfi_restriction_run_busy);
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static DEVICE_ATTR_RW(rfi_restriction_err_code);
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static DEVICE_ATTR_RW(rfi_restriction_data_rate);
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static DEVICE_ATTR_RO(ddr_data_rate_point_0);
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static DEVICE_ATTR_RO(ddr_data_rate_point_1);
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static DEVICE_ATTR_RO(ddr_data_rate_point_2);
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static DEVICE_ATTR_RO(ddr_data_rate_point_3);
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static DEVICE_ATTR_RW(rfi_disable);
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static ssize_t rfi_restriction_store(struct device *dev,
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struct device_attribute *attr,
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const char *buf, size_t count)
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{
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u16 id = 0x0008;
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u32 input;
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int ret;
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ret = kstrtou32(buf, 10, &input);
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if (ret)
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return ret;
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ret = processor_thermal_send_mbox_write_cmd(to_pci_dev(dev), id, input);
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if (ret)
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return ret;
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return count;
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}
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static ssize_t rfi_restriction_show(struct device *dev,
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struct device_attribute *attr,
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char *buf)
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{
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u16 id = 0x0007;
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u64 resp;
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int ret;
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ret = processor_thermal_send_mbox_read_cmd(to_pci_dev(dev), id, &resp);
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if (ret)
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return ret;
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return sprintf(buf, "%llu\n", resp);
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}
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static ssize_t ddr_data_rate_show(struct device *dev,
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struct device_attribute *attr,
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char *buf)
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{
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u16 id = 0x0107;
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u64 resp;
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int ret;
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ret = processor_thermal_send_mbox_read_cmd(to_pci_dev(dev), id, &resp);
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if (ret)
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return ret;
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return sprintf(buf, "%llu\n", resp);
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}
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static DEVICE_ATTR_RW(rfi_restriction);
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static DEVICE_ATTR_RO(ddr_data_rate);
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static struct attribute *dvfs_attrs[] = {
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&dev_attr_rfi_restriction_run_busy.attr,
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&dev_attr_rfi_restriction_err_code.attr,
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&dev_attr_rfi_restriction_data_rate.attr,
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&dev_attr_ddr_data_rate_point_0.attr,
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&dev_attr_ddr_data_rate_point_1.attr,
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&dev_attr_ddr_data_rate_point_2.attr,
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&dev_attr_ddr_data_rate_point_3.attr,
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&dev_attr_rfi_disable.attr,
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&dev_attr_ddr_data_rate.attr,
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&dev_attr_rfi_restriction.attr,
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NULL
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};
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static const struct attribute_group dvfs_attribute_group = {
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.attrs = dvfs_attrs,
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.name = "dvfs"
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};
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int proc_thermal_rfim_add(struct pci_dev *pdev, struct proc_thermal_device *proc_priv)
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{
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int ret;
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if (proc_priv->mmio_feature_mask & PROC_THERMAL_FEATURE_FIVR) {
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ret = sysfs_create_group(&pdev->dev.kobj, &fivr_attribute_group);
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if (ret)
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return ret;
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}
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if (proc_priv->mmio_feature_mask & PROC_THERMAL_FEATURE_DVFS) {
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ret = sysfs_create_group(&pdev->dev.kobj, &dvfs_attribute_group);
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if (ret && proc_priv->mmio_feature_mask & PROC_THERMAL_FEATURE_FIVR) {
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sysfs_remove_group(&pdev->dev.kobj, &fivr_attribute_group);
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return ret;
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}
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}
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return 0;
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}
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EXPORT_SYMBOL_GPL(proc_thermal_rfim_add);
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void proc_thermal_rfim_remove(struct pci_dev *pdev)
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{
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struct proc_thermal_device *proc_priv = pci_get_drvdata(pdev);
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if (proc_priv->mmio_feature_mask & PROC_THERMAL_FEATURE_FIVR)
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sysfs_remove_group(&pdev->dev.kobj, &fivr_attribute_group);
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if (proc_priv->mmio_feature_mask & PROC_THERMAL_FEATURE_DVFS)
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sysfs_remove_group(&pdev->dev.kobj, &dvfs_attribute_group);
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}
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EXPORT_SYMBOL_GPL(proc_thermal_rfim_remove);
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MODULE_LICENSE("GPL v2");
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