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linux/arch
Zhangjin Wu c828856b51
riscv: enable HAVE_LD_DEAD_CODE_DATA_ELIMINATION
Select CONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION for RISC-V, allowing
the user to enable dead code elimination. In order for this to work,
ensure that we keep the alternative table by annotating them with KEEP.

This boots well on qemu with both rv32_defconfig & rv64 defconfig, but
it only shrinks their builds by ~1%, a smaller config is thereforce
customized to test this feature:

          | rv32                   | rv64
  --------|------------------------|---------------------
   No DCE | 4460684                | 4893488
      DCE | 3986716                | 4376400
   Shrink |  473968 (~10.6%)       |  517088 (~10.5%)

The config used above only reserves necessary options to boot on qemu
with serial console, more like the size-critical embedded scenes:

  - rv64 config: https://pastebin.com/crz82T0s
  - rv32 config: rv64 config + 32-bit.config

Here is Jisheng's original commit-msg:
When trying to run linux with various opensource riscv core on
resource limited FPGA platforms, for example, those FPGAs with less
than 16MB SDRAM, I want to save mem as much as possible. One of the
major technologies is kernel size optimizations, I found that riscv
does not currently support HAVE_LD_DEAD_CODE_DATA_ELIMINATION, which
passes -fdata-sections, -ffunction-sections to CFLAGS and passes the
--gc-sections flag to the linker.

This not only benefits my case on FPGA but also benefits defconfigs.
Here are some notable improvements from enabling this with defconfigs:

nommu_k210_defconfig:
   text    data     bss     dec     hex
1112009  410288   59837 1582134  182436     before
 962838  376656   51285 1390779  1538bb     after

rv32_defconfig:
   text    data     bss     dec     hex
8804455 2816544  290577 11911576 b5c198     before
8692295 2779872  288977 11761144 b375f8     after

defconfig:
   text    data     bss     dec     hex
9438267 3391332  485333 13314932 cb2b74     before
9285914 3350052  483349 13119315 c82f53     after

Signed-off-by: Zhangjin Wu <falcon@tinylab.org>
Co-developed-by: Jisheng Zhang <jszhang@kernel.org>
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
Reviewed-by: Guo Ren <guoren@kernel.org>
Tested-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Tested-by: Nick Desaulniers <ndesaulniers@google.com> # build
Link: https://lore.kernel.org/r/20230523165502.2592-5-jszhang@kernel.org
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-06-25 16:24:05 -07:00
..
alpha Locking changes in v6.4: 2023-05-05 12:56:55 -07:00
arc Locking changes in v6.4: 2023-05-05 12:56:55 -07:00
arm Locking changes in v6.4: 2023-05-05 12:56:55 -07:00
arm64 Locking changes in v6.4: 2023-05-05 12:56:55 -07:00
csky arch/csky patches for 6.4 2023-05-04 12:25:05 -07:00
hexagon Locking changes in v6.4: 2023-05-05 12:56:55 -07:00
ia64 Locking changes in v6.4: 2023-05-05 12:56:55 -07:00
loongarch Locking changes in v6.4: 2023-05-05 12:56:55 -07:00
m68k Locking changes in v6.4: 2023-05-05 12:56:55 -07:00
microblaze Kconfig: introduce HAS_IOPORT option and select it as necessary 2023-04-05 22:15:19 +02:00
mips Locking changes in v6.4: 2023-05-05 12:56:55 -07:00
nios2 - Nick Piggin's "shoot lazy tlbs" series, to improve the peformance of 2023-04-27 19:42:02 -07:00
openrisc Locking changes in v6.4: 2023-05-05 12:56:55 -07:00
parisc Locking changes in v6.4: 2023-05-05 12:56:55 -07:00
powerpc Locking changes in v6.4: 2023-05-05 12:56:55 -07:00
riscv riscv: enable HAVE_LD_DEAD_CODE_DATA_ELIMINATION 2023-06-25 16:24:05 -07:00
s390 s390: remove the unneeded select GCC12_NO_ARRAY_BOUNDS 2023-05-05 18:56:23 -07:00
sh Locking changes in v6.4: 2023-05-05 12:56:55 -07:00
sparc Locking changes in v6.4: 2023-05-05 12:56:55 -07:00
um This pull request contains the following changes for UML: 2023-05-03 19:02:03 -07:00
x86 Locking changes in v6.4: 2023-05-05 12:56:55 -07:00
xtensa Locking changes in v6.4: 2023-05-05 12:56:55 -07:00
.gitignore
Kconfig lazy tlb: shoot lazies, non-refcounting lazy tlb mm reference handling scheme 2023-03-28 16:20:08 -07:00