-----BEGIN PGP SIGNATURE----- iQIcBAABAgAGBQJd3YntAAoJEAx081l5xIa+dcQP/ikABkpm+q23FLKteRpL1rtX xqlg5+KHW+YVCDls2BrINF6vYzyisoa8fNPlKMmOHse/IgMhFe9vBbCj1KQQOUR1 apNycI1wrcw/mn2WDikoIcF6C5cjqK9YVknnYoM6HnF1VmpGd1ecSGrOHrunEkrK cMAWYIeqWGU8Gj/HUOitAFpLWFUMNle0BJuRoGLcoMusgS8yuCIEcpNzRhgL8fvJ bW4imuyv24OjPoQzbKD0oQ0VIP86H0eM4LIeGZ2uyK/BSPKmMDqI4z4isUheS7RL w4a6BdobMIdhew5dBXS0LsUJ3JniVJdHy123q9KgpmQAhGpiNoLT6BujfoUTUeWx Mu0vM8Xmv9n4npdBYC+fLEFQXYJlu9uBA490jP84Kz6Fg1c6GyBebDY7/c2O4Zmg 7pvygmUF6boD6v2sIC/3161crgwU4g8zoxm2V4i9naxes2QB13LiEuJWlaI/FdxY fd3zpglFGdoF1ThNne4QDh6gMKpXvjITyu/QxZeZ67Dt6i0Aqw9cRGHSpiVhYyDc cx2hAp+rDvUi5SHkJKFpVImjB2DDn2xUG2uFMHz0cy9wNg203L3fRDi0hVtnM1+W VpCxyLs2Upz6kEjDRVsfMZ9chCcWAWpVuKhtuuMUDw/IKnbP3uV8kzgJpVpaRVkD 76s5uYWHHBlk1IVlkOUP =Hj7G -----END PGP SIGNATURE----- Merge tag 'drm-next-2019-11-27' of git://anongit.freedesktop.org/drm/drm Pull drm updates from Dave Airlie: "Lots of stuff in here, though it hasn't been too insane this merge apart from dealing with the security fun. uapi: - export different colorspace properties on DP vs HDMI - new fourcc for ARM 16x16 block format - syncobj: allow querying last submitted timeline value - DRM_FORMAT_BIG_ENDIAN defined as unsigned core: - allow using gem vma manager in ttm - connector/encoder/bridge doc fixes - allow more than 3 encoders for a connector - displayport mst suspend/resume reprobing support - vram lazy unmapping, uniform vram mm and gem vram - edid cleanups + AVI informframe bar info - displayport helpers - dpcd parser added dp_cec: - Allow a connector to be associated with a cec device ttm: - pipelining with no_gpu_wait fix - always keep BOs on the LRU sched: - allow free_job routine to sleep i915: - Block userptr from mappable GTT - i915 perf uapi versioning - OA stream dynamic reconfiguration - make context persistence optional - introduce DRM_I915_UNSTABLE Kconfig - add fake lmem testing under unstable - BT.2020 support for DP MSA - struct mutex elimination - Tigerlake display/PLL/power management improvements - Jasper Lake PCH support - refactor PMU for multiple GPUs - Icelake firmware update - Split out vga + switcheroo code amdgpu: - implement dma-buf import/export without helpers - vega20 RAS enablement - DC i2c over aux fixes - renoir GPU reset - DC HDCP support - BACO support for CI/VI asics - MSI-X support - Arcturus EEPROM support - Arcturus VCN encode support - VCN dynamic powergating on RV/RV2 amdkfd: - add navi12/14/renoir support to kfd radeon: - SI dpm fix ported from amdgpu - fix bad DMA on ppc platforms gma500: - memory leak fixes qxl: - convert to new gem mmap exynos: - build warning fix komeda: - add aclk sysfs attribute v3d: - userspace cleanup uapi change i810: - fix for underflow in dispatch ioctls ast: - refactor show_cursor mgag200: - refactor show_cursor arcgpu: - encoder finding improvements mediatek: - mipi_tx, dsi and partial crtc support for MT8183 SoC - rotation support meson: - add suspend/resume support omap: - misc refactors tegra: - DisplayPort support for Tegra 210, 186 and 194. - IOMMU-backed DMA API fixes panfrost: - fix lockdep issue - simplify devfreq integration rcar-du: - R8A774B1 SoC support - fixes for H2 ES2.0 sun4i: - vcc-dsi regulator support virtio-gpu: - vmexit vs spinlock fix - move to gem shmem helpers - handle large command buffers with cma" * tag 'drm-next-2019-11-27' of git://anongit.freedesktop.org/drm/drm: (1855 commits) drm/amdgpu: invalidate mmhub semaphore workaround in gmc9/gmc10 drm/amdgpu: initialize vm_inv_eng0_sem for gfxhub and mmhub drm/amd/amdgpu/sriov skip RLCG s/r list for arcturus VF. drm/amd/amdgpu/sriov temporarily skip ras,dtm,hdcp for arcturus VF drm/amdgpu/gfx10: re-init clear state buffer after gpu reset merge fix for "ftrace: Rework event_create_dir()" drm/amdgpu: Update Arcturus golden registers drm/amdgpu/gfx10: fix out-of-bound mqd_backup array access drm/amdgpu/gfx10: explicitly wait for cp idle after halt/unhalt Revert "drm/amd/display: enable S/G for RAVEN chip" drm/amdgpu: disable gfxoff on original raven drm/amdgpu: remove experimental flag for Navi14 drm/amdgpu: disable gfxoff when using register read interface drm/amdgpu/powerplay: properly set PP_GFXOFF_MASK (v2) drm/amdgpu: fix bad DMA from INTERRUPT_CNTL2 drm/radeon: fix bad DMA from INTERRUPT_CNTL2 drm/amd/display: Fix debugfs on MST connectors drm/amdgpu/nv: add asic func for fetching vbios from rom directly drm/amdgpu: put flush_delayed_work at first drm/amdgpu/vcn2.5: fix the enc loop with hw fini ...
190 lines
4.3 KiB
C
190 lines
4.3 KiB
C
/*
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* SPDX-License-Identifier: MIT
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*
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* Copyright © 2014-2018 Intel Corporation
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*/
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#include "gem/i915_gem_object.h"
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#include "i915_drv.h"
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#include "intel_engine_pm.h"
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#include "intel_engine_pool.h"
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static struct intel_engine_cs *to_engine(struct intel_engine_pool *pool)
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{
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return container_of(pool, struct intel_engine_cs, pool);
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}
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static struct list_head *
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bucket_for_size(struct intel_engine_pool *pool, size_t sz)
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{
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int n;
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/*
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* Compute a power-of-two bucket, but throw everything greater than
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* 16KiB into the same bucket: i.e. the buckets hold objects of
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* (1 page, 2 pages, 4 pages, 8+ pages).
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*/
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n = fls(sz >> PAGE_SHIFT) - 1;
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if (n >= ARRAY_SIZE(pool->cache_list))
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n = ARRAY_SIZE(pool->cache_list) - 1;
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return &pool->cache_list[n];
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}
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static void node_free(struct intel_engine_pool_node *node)
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{
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i915_gem_object_put(node->obj);
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i915_active_fini(&node->active);
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kfree(node);
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}
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static int pool_active(struct i915_active *ref)
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{
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struct intel_engine_pool_node *node =
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container_of(ref, typeof(*node), active);
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struct dma_resv *resv = node->obj->base.resv;
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int err;
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if (dma_resv_trylock(resv)) {
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dma_resv_add_excl_fence(resv, NULL);
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dma_resv_unlock(resv);
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}
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err = i915_gem_object_pin_pages(node->obj);
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if (err)
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return err;
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/* Hide this pinned object from the shrinker until retired */
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i915_gem_object_make_unshrinkable(node->obj);
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return 0;
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}
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__i915_active_call
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static void pool_retire(struct i915_active *ref)
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{
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struct intel_engine_pool_node *node =
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container_of(ref, typeof(*node), active);
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struct intel_engine_pool *pool = node->pool;
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struct list_head *list = bucket_for_size(pool, node->obj->base.size);
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unsigned long flags;
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GEM_BUG_ON(!intel_engine_pm_is_awake(to_engine(pool)));
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i915_gem_object_unpin_pages(node->obj);
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/* Return this object to the shrinker pool */
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i915_gem_object_make_purgeable(node->obj);
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spin_lock_irqsave(&pool->lock, flags);
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list_add(&node->link, list);
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spin_unlock_irqrestore(&pool->lock, flags);
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}
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static struct intel_engine_pool_node *
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node_create(struct intel_engine_pool *pool, size_t sz)
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{
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struct intel_engine_cs *engine = to_engine(pool);
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struct intel_engine_pool_node *node;
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struct drm_i915_gem_object *obj;
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node = kmalloc(sizeof(*node),
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GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_NOWARN);
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if (!node)
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return ERR_PTR(-ENOMEM);
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node->pool = pool;
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i915_active_init(&node->active, pool_active, pool_retire);
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obj = i915_gem_object_create_internal(engine->i915, sz);
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if (IS_ERR(obj)) {
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i915_active_fini(&node->active);
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kfree(node);
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return ERR_CAST(obj);
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}
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i915_gem_object_set_readonly(obj);
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node->obj = obj;
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return node;
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}
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static struct intel_engine_pool *lookup_pool(struct intel_engine_cs *engine)
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{
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if (intel_engine_is_virtual(engine))
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engine = intel_virtual_engine_get_sibling(engine, 0);
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GEM_BUG_ON(!engine);
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return &engine->pool;
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}
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struct intel_engine_pool_node *
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intel_engine_get_pool(struct intel_engine_cs *engine, size_t size)
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{
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struct intel_engine_pool *pool = lookup_pool(engine);
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struct intel_engine_pool_node *node;
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struct list_head *list;
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unsigned long flags;
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int ret;
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GEM_BUG_ON(!intel_engine_pm_is_awake(to_engine(pool)));
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size = PAGE_ALIGN(size);
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list = bucket_for_size(pool, size);
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spin_lock_irqsave(&pool->lock, flags);
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list_for_each_entry(node, list, link) {
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if (node->obj->base.size < size)
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continue;
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list_del(&node->link);
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break;
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}
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spin_unlock_irqrestore(&pool->lock, flags);
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if (&node->link == list) {
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node = node_create(pool, size);
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if (IS_ERR(node))
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return node;
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}
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ret = i915_active_acquire(&node->active);
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if (ret) {
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node_free(node);
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return ERR_PTR(ret);
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}
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return node;
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}
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void intel_engine_pool_init(struct intel_engine_pool *pool)
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{
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int n;
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spin_lock_init(&pool->lock);
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for (n = 0; n < ARRAY_SIZE(pool->cache_list); n++)
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INIT_LIST_HEAD(&pool->cache_list[n]);
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}
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void intel_engine_pool_park(struct intel_engine_pool *pool)
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{
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int n;
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for (n = 0; n < ARRAY_SIZE(pool->cache_list); n++) {
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struct list_head *list = &pool->cache_list[n];
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struct intel_engine_pool_node *node, *nn;
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list_for_each_entry_safe(node, nn, list, link)
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node_free(node);
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INIT_LIST_HEAD(list);
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}
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}
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void intel_engine_pool_fini(struct intel_engine_pool *pool)
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{
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int n;
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for (n = 0; n < ARRAY_SIZE(pool->cache_list); n++)
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GEM_BUG_ON(!list_empty(&pool->cache_list[n]));
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}
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