ccdfbfec9e
Convert RAS and FRU code to use the 19-bit I2C memory address and remove all "slave_addr", as this is now absolved into the 19-bit address. Cc: Jean Delvare <jdelvare@suse.de> Cc: John Clements <john.clements@amd.com> Cc: Alexander Deucher <Alexander.Deucher@amd.com> Cc: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com> Cc: Lijo Lazar <Lijo.Lazar@amd.com> Cc: Stanley Yang <Stanley.Yang@amd.com> Cc: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Luben Tuikov <luben.tuikov@amd.com> Acked-by: Alexander Deucher <Alexander.Deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
94 lines
2.7 KiB
C
94 lines
2.7 KiB
C
/*
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* Copyright 2019 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef _AMDGPU_RAS_EEPROM_H
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#define _AMDGPU_RAS_EEPROM_H
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#include <linux/i2c.h>
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struct amdgpu_device;
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enum amdgpu_ras_eeprom_err_type{
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AMDGPU_RAS_EEPROM_ERR_PLACE_HOLDER,
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AMDGPU_RAS_EEPROM_ERR_RECOVERABLE,
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AMDGPU_RAS_EEPROM_ERR_NON_RECOVERABLE
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};
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struct amdgpu_ras_eeprom_table_header {
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uint32_t header;
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uint32_t version;
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uint32_t first_rec_offset;
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uint32_t tbl_size;
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uint32_t checksum;
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}__attribute__((__packed__));
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struct amdgpu_ras_eeprom_control {
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struct amdgpu_ras_eeprom_table_header tbl_hdr;
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u32 i2c_address; /* Base I2C 19-bit memory address */
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uint32_t next_addr;
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unsigned int num_recs;
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struct mutex tbl_mutex;
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uint32_t tbl_byte_sum;
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};
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/*
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* Represents single table record. Packed to be easily serialized into byte
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* stream.
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*/
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struct eeprom_table_record {
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union {
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uint64_t address;
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uint64_t offset;
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};
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uint64_t retired_page;
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uint64_t ts;
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enum amdgpu_ras_eeprom_err_type err_type;
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union {
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unsigned char bank;
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unsigned char cu;
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};
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unsigned char mem_channel;
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unsigned char mcumc_id;
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}__attribute__((__packed__));
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int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control,
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bool *exceed_err_limit);
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int amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control *control);
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bool amdgpu_ras_eeprom_check_err_threshold(struct amdgpu_device *adev);
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int amdgpu_ras_eeprom_process_recods(struct amdgpu_ras_eeprom_control *control,
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struct eeprom_table_record *records,
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bool write,
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int num);
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inline uint32_t amdgpu_ras_eeprom_get_record_max_length(void);
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void amdgpu_ras_eeprom_test(struct amdgpu_ras_eeprom_control *control);
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#endif // _AMDGPU_RAS_EEPROM_H
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