Yang Wang cd3a49af58 drm/amdgpu: change the alignment size of TMR BO to 1M ... align TMR BO size TO tmr size is not necessary, modify the size to 1M to avoid re-create BO fail when serious VRAM fragmentation. v2: add new macro PSP_TMR_ALIGNMENT for TMR BO alignment size Signed-off-by: Yang Wang <KevinYang.Wang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2022-09-13 12:56:16 -04:00
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acp	drm: amd/acp: fix broken menu structure	2020-03-13 11:52:35 -04:00
amdgpu	drm/amdgpu: change the alignment size of TMR BO to 1M	2022-09-13 12:56:16 -04:00
amdkfd	drm/amdkfd: Remove prefault before migrating to VRAM	2022-09-13 12:54:23 -04:00
display	drm/amd/display: update header files	2022-09-13 12:56:08 -04:00
include	drm/amd/amdgpu: update GC 10.3.0 pwrdec	2022-09-13 12:54:23 -04:00
pm	drm/amd/pm: disable BACO entry/exit completely on several sienna cichlid cards	2022-09-13 12:54:22 -04:00