856732adc1
Engicam i.Core STM32MP1 EDIMM2.2 Starter Kit has plugged with 7" LVDS panel. Engicam i.Core STM32MP1 SoM has SN65DSI84 DSI to LVDS bridge. This patch adds a display pipeline to connect DSI to SN65DSI84 to 7" LVDS panel. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
132 lines
2.4 KiB
Text
132 lines
2.4 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* Copyright (c) STMicroelectronics 2019 - All Rights Reserved
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* Copyright (c) 2020 Engicam srl
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* Copyright (c) 2020 Amarula Solutons(India)
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*/
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/dts-v1/;
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#include "stm32mp157.dtsi"
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#include "stm32mp157a-icore-stm32mp1.dtsi"
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#include "stm32mp15-pinctrl.dtsi"
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#include "stm32mp15xxaa-pinctrl.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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/ {
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model = "Engicam i.Core STM32MP1 EDIMM2.2 Starter Kit";
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compatible = "engicam,icore-stm32mp1-edimm2.2",
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"engicam,icore-stm32mp1", "st,stm32mp157";
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aliases {
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serial0 = &uart4;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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backlight: backlight {
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compatible = "gpio-backlight";
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gpios = <&gpiod 13 GPIO_ACTIVE_HIGH>;
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default-on;
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};
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panel {
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compatible = "yes-optoelectronics,ytc700tlag-05-201c";
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backlight = <&backlight>;
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power-supply = <&v3v3>;
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port {
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panel_out_bridge: endpoint {
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remote-endpoint = <&bridge_out_panel>;
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};
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};
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};
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};
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&dsi {
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status = "okay";
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phy-dsi-supply = <®18>;
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ports {
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port@0 {
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reg = <0>;
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dsi_in_ltdc: endpoint {
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remote-endpoint = <<dc_out_dsi>;
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};
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};
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port@1 {
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reg = <1>;
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dsi_out_bridge: endpoint {
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remote-endpoint = <&bridge_in_dsi>;
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};
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};
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};
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};
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&i2c6 {
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i2c-scl-falling-time-ns = <20>;
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i2c-scl-rising-time-ns = <185>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&i2c6_pins_a>;
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pinctrl-1 = <&i2c6_sleep_pins_a>;
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status = "okay";
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bridge@2c {
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compatible = "ti,sn65dsi84";
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reg = <0x2c>;
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enable-gpios = <&gpiof 15 GPIO_ACTIVE_HIGH>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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bridge_in_dsi: endpoint {
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remote-endpoint = <&dsi_out_bridge>;
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data-lanes = <1 2>;
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};
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};
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port@2 {
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reg = <2>;
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bridge_out_panel: endpoint {
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remote-endpoint = <&panel_out_bridge>;
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};
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};
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};
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};
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};
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<dc {
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status = "okay";
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port {
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ltdc_out_dsi: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&dsi_in_ltdc>;
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};
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};
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};
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&sdmmc1 {
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bus-width = <4>;
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disable-wp;
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pinctrl-names = "default", "opendrain", "sleep";
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pinctrl-0 = <&sdmmc1_b4_pins_a>;
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pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
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pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
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st,neg-edge;
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vmmc-supply = <&v3v3>;
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status = "okay";
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};
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&uart4 {
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pinctrl-names = "default", "sleep", "idle";
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pinctrl-0 = <&uart4_pins_a>;
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pinctrl-1 = <&uart4_sleep_pins_a>;
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pinctrl-2 = <&uart4_idle_pins_a>;
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status = "okay";
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};
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