62b95a7b44
In a subsequent patch, we will relax the kernel mode NEON policy, and permit kernel mode NEON to be used not only from task context, as is permitted today, but also from softirq context. Given that softirqs may trigger over the back of any IRQ unless they are explicitly disabled, we need to address the resulting races in the VFP state handling, by disabling softirq processing in two distinct but related cases: - kernel mode NEON will leave the FPU disabled after it completes, so any kernel code sequence that enables the FPU and subsequently accesses its registers needs to disable softirqs until it completes; - kernel_neon_begin() will preserve the userland VFP state in memory, and if it interrupts the ordinary VFP state preserve sequence, the latter will resume execution with the VFP registers corrupted, and happily continue saving them to memory. Given that disabling softirqs also disables preemption, we can replace the existing preempt_disable/enable occurrences in the VFP state handling asm code with new macros that dis/enable softirqs instead. In the VFP state handling C code, add local_bh_disable/enable() calls in those places where the VFP state is preserved. One thing to keep in mind is that, once we allow NEON use in softirq context, the result of any such interruption is that the FPEXC_EN bit in the FPEXC register will be cleared, and vfp_current_hw_state[cpu] will be NULL. This means that any sequence that [conditionally] clears FPEXC_EN and/or sets vfp_current_hw_state[cpu] to NULL does not need to run with softirqs disabled, as the result will be the same. Furthermore, the handling of THREAD_NOTIFY_SWITCH is guaranteed to run with IRQs disabled, and so it does not need protection from softirq interruptions either. Tested-by: Martin Willi <martin@strongswan.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
790 lines
17 KiB
C
790 lines
17 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* arch/arm/include/asm/assembler.h
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*
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* Copyright (C) 1996-2000 Russell King
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*
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* This file contains arm architecture specific defines
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* for the different processors.
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*
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* Do not include any C declarations in this file - it is included by
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* assembler source.
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*/
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#ifndef __ASM_ASSEMBLER_H__
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#define __ASM_ASSEMBLER_H__
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#ifndef __ASSEMBLY__
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#error "Only include this from assembly code"
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#endif
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#include <asm/ptrace.h>
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#include <asm/opcodes-virt.h>
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#include <asm/asm-offsets.h>
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#include <asm/page.h>
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#include <asm/thread_info.h>
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#include <asm/uaccess-asm.h>
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#define IOMEM(x) (x)
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/*
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* Endian independent macros for shifting bytes within registers.
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*/
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#ifndef __ARMEB__
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#define lspull lsr
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#define lspush lsl
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#define get_byte_0 lsl #0
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#define get_byte_1 lsr #8
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#define get_byte_2 lsr #16
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#define get_byte_3 lsr #24
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#define put_byte_0 lsl #0
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#define put_byte_1 lsl #8
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#define put_byte_2 lsl #16
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#define put_byte_3 lsl #24
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#else
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#define lspull lsl
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#define lspush lsr
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#define get_byte_0 lsr #24
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#define get_byte_1 lsr #16
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#define get_byte_2 lsr #8
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#define get_byte_3 lsl #0
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#define put_byte_0 lsl #24
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#define put_byte_1 lsl #16
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#define put_byte_2 lsl #8
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#define put_byte_3 lsl #0
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#endif
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/* Select code for any configuration running in BE8 mode */
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#ifdef CONFIG_CPU_ENDIAN_BE8
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#define ARM_BE8(code...) code
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#else
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#define ARM_BE8(code...)
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#endif
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/*
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* Data preload for architectures that support it
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*/
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#if __LINUX_ARM_ARCH__ >= 5
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#define PLD(code...) code
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#else
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#define PLD(code...)
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#endif
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/*
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* This can be used to enable code to cacheline align the destination
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* pointer when bulk writing to memory. Experiments on StrongARM and
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* XScale didn't show this a worthwhile thing to do when the cache is not
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* set to write-allocate (this would need further testing on XScale when WA
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* is used).
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*
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* On Feroceon there is much to gain however, regardless of cache mode.
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*/
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#ifdef CONFIG_CPU_FEROCEON
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#define CALGN(code...) code
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#else
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#define CALGN(code...)
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#endif
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#define IMM12_MASK 0xfff
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/* the frame pointer used for stack unwinding */
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ARM( fpreg .req r11 )
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THUMB( fpreg .req r7 )
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/*
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* Enable and disable interrupts
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*/
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#if __LINUX_ARM_ARCH__ >= 6
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.macro disable_irq_notrace
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cpsid i
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.endm
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.macro enable_irq_notrace
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cpsie i
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.endm
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#else
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.macro disable_irq_notrace
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msr cpsr_c, #PSR_I_BIT | SVC_MODE
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.endm
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.macro enable_irq_notrace
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msr cpsr_c, #SVC_MODE
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.endm
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#endif
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#if __LINUX_ARM_ARCH__ < 7
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.macro dsb, args
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mcr p15, 0, r0, c7, c10, 4
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.endm
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.macro isb, args
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mcr p15, 0, r0, c7, c5, 4
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.endm
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#endif
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.macro asm_trace_hardirqs_off, save=1
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#if defined(CONFIG_TRACE_IRQFLAGS)
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.if \save
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stmdb sp!, {r0-r3, ip, lr}
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.endif
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bl trace_hardirqs_off
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.if \save
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ldmia sp!, {r0-r3, ip, lr}
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.endif
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#endif
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.endm
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.macro asm_trace_hardirqs_on, cond=al, save=1
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#if defined(CONFIG_TRACE_IRQFLAGS)
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/*
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* actually the registers should be pushed and pop'd conditionally, but
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* after bl the flags are certainly clobbered
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*/
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.if \save
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stmdb sp!, {r0-r3, ip, lr}
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.endif
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bl\cond trace_hardirqs_on
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.if \save
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ldmia sp!, {r0-r3, ip, lr}
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.endif
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#endif
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.endm
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.macro disable_irq, save=1
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disable_irq_notrace
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asm_trace_hardirqs_off \save
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.endm
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.macro enable_irq
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asm_trace_hardirqs_on
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enable_irq_notrace
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.endm
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/*
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* Save the current IRQ state and disable IRQs. Note that this macro
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* assumes FIQs are enabled, and that the processor is in SVC mode.
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*/
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.macro save_and_disable_irqs, oldcpsr
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#ifdef CONFIG_CPU_V7M
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mrs \oldcpsr, primask
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#else
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mrs \oldcpsr, cpsr
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#endif
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disable_irq
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.endm
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.macro save_and_disable_irqs_notrace, oldcpsr
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#ifdef CONFIG_CPU_V7M
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mrs \oldcpsr, primask
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#else
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mrs \oldcpsr, cpsr
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#endif
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disable_irq_notrace
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.endm
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/*
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* Restore interrupt state previously stored in a register. We don't
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* guarantee that this will preserve the flags.
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*/
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.macro restore_irqs_notrace, oldcpsr
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#ifdef CONFIG_CPU_V7M
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msr primask, \oldcpsr
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#else
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msr cpsr_c, \oldcpsr
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#endif
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.endm
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.macro restore_irqs, oldcpsr
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tst \oldcpsr, #PSR_I_BIT
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asm_trace_hardirqs_on cond=eq
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restore_irqs_notrace \oldcpsr
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.endm
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/*
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* Assembly version of "adr rd, BSYM(sym)". This should only be used to
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* reference local symbols in the same assembly file which are to be
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* resolved by the assembler. Other usage is undefined.
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*/
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.irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo
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.macro badr\c, rd, sym
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#ifdef CONFIG_THUMB2_KERNEL
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adr\c \rd, \sym + 1
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#else
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adr\c \rd, \sym
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#endif
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.endm
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.endr
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/*
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* Get current thread_info.
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*/
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.macro get_thread_info, rd
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/* thread_info is the first member of struct task_struct */
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get_current \rd
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.endm
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/*
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* Increment/decrement the preempt count.
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*/
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#ifdef CONFIG_PREEMPT_COUNT
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.macro inc_preempt_count, ti, tmp
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ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count
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add \tmp, \tmp, #1 @ increment it
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str \tmp, [\ti, #TI_PREEMPT]
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.endm
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.macro dec_preempt_count, ti, tmp
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ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count
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sub \tmp, \tmp, #1 @ decrement it
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str \tmp, [\ti, #TI_PREEMPT]
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.endm
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#else
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.macro inc_preempt_count, ti, tmp
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.endm
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.macro dec_preempt_count, ti, tmp
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.endm
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#endif
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.macro local_bh_disable, ti, tmp
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ldr \tmp, [\ti, #TI_PREEMPT]
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add \tmp, \tmp, #SOFTIRQ_DISABLE_OFFSET
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str \tmp, [\ti, #TI_PREEMPT]
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.endm
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.macro local_bh_enable_ti, ti, tmp
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get_thread_info \ti
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ldr \tmp, [\ti, #TI_PREEMPT]
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sub \tmp, \tmp, #SOFTIRQ_DISABLE_OFFSET
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str \tmp, [\ti, #TI_PREEMPT]
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.endm
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#define USERL(l, x...) \
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9999: x; \
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.pushsection __ex_table,"a"; \
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.align 3; \
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.long 9999b,l; \
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.popsection
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#define USER(x...) USERL(9001f, x)
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#ifdef CONFIG_SMP
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#define ALT_SMP(instr...) \
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9998: instr
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/*
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* Note: if you get assembler errors from ALT_UP() when building with
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* CONFIG_THUMB2_KERNEL, you almost certainly need to use
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* ALT_SMP( W(instr) ... )
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*/
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#define ALT_UP(instr...) \
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.pushsection ".alt.smp.init", "a" ;\
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.align 2 ;\
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.long 9998b - . ;\
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9997: instr ;\
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.if . - 9997b == 2 ;\
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nop ;\
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.endif ;\
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.if . - 9997b != 4 ;\
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.error "ALT_UP() content must assemble to exactly 4 bytes";\
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.endif ;\
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.popsection
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#define ALT_UP_B(label) \
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.pushsection ".alt.smp.init", "a" ;\
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.align 2 ;\
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.long 9998b - . ;\
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W(b) . + (label - 9998b) ;\
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.popsection
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#else
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#define ALT_SMP(instr...)
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#define ALT_UP(instr...) instr
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#define ALT_UP_B(label) b label
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#endif
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/*
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* this_cpu_offset - load the per-CPU offset of this CPU into
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* register 'rd'
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*/
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.macro this_cpu_offset, rd:req
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#ifdef CONFIG_SMP
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ALT_SMP(mrc p15, 0, \rd, c13, c0, 4)
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#ifdef CONFIG_CPU_V6
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ALT_UP_B(.L1_\@)
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.L0_\@:
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.subsection 1
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.L1_\@: ldr_va \rd, __per_cpu_offset
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b .L0_\@
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.previous
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#endif
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#else
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mov \rd, #0
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#endif
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.endm
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/*
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* set_current - store the task pointer of this CPU's current task
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*/
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.macro set_current, rn:req, tmp:req
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#if defined(CONFIG_CURRENT_POINTER_IN_TPIDRURO) || defined(CONFIG_SMP)
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9998: mcr p15, 0, \rn, c13, c0, 3 @ set TPIDRURO register
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#ifdef CONFIG_CPU_V6
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ALT_UP_B(.L0_\@)
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.subsection 1
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.L0_\@: str_va \rn, __current, \tmp
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b .L1_\@
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.previous
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.L1_\@:
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#endif
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#else
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str_va \rn, __current, \tmp
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#endif
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.endm
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/*
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* get_current - load the task pointer of this CPU's current task
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*/
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.macro get_current, rd:req
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#if defined(CONFIG_CURRENT_POINTER_IN_TPIDRURO) || defined(CONFIG_SMP)
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9998: mrc p15, 0, \rd, c13, c0, 3 @ get TPIDRURO register
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#ifdef CONFIG_CPU_V6
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ALT_UP_B(.L0_\@)
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.subsection 1
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.L0_\@: ldr_va \rd, __current
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b .L1_\@
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.previous
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.L1_\@:
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#endif
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#else
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ldr_va \rd, __current
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#endif
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.endm
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/*
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* reload_current - reload the task pointer of this CPU's current task
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* into the TLS register
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*/
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.macro reload_current, t1:req, t2:req
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#if defined(CONFIG_CURRENT_POINTER_IN_TPIDRURO) || defined(CONFIG_SMP)
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#ifdef CONFIG_CPU_V6
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ALT_SMP(nop)
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ALT_UP_B(.L0_\@)
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#endif
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ldr_this_cpu \t1, __entry_task, \t1, \t2
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mcr p15, 0, \t1, c13, c0, 3 @ store in TPIDRURO
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.L0_\@:
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#endif
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.endm
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/*
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* Instruction barrier
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*/
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.macro instr_sync
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#if __LINUX_ARM_ARCH__ >= 7
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isb
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#elif __LINUX_ARM_ARCH__ == 6
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mcr p15, 0, r0, c7, c5, 4
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#endif
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.endm
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/*
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* SMP data memory barrier
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*/
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.macro smp_dmb mode
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#ifdef CONFIG_SMP
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#if __LINUX_ARM_ARCH__ >= 7
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.ifeqs "\mode","arm"
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ALT_SMP(dmb ish)
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.else
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ALT_SMP(W(dmb) ish)
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.endif
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#elif __LINUX_ARM_ARCH__ == 6
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ALT_SMP(mcr p15, 0, r0, c7, c10, 5) @ dmb
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#else
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#error Incompatible SMP platform
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#endif
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.ifeqs "\mode","arm"
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ALT_UP(nop)
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.else
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ALT_UP(W(nop))
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.endif
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#endif
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.endm
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#if defined(CONFIG_CPU_V7M)
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/*
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* setmode is used to assert to be in svc mode during boot. For v7-M
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* this is done in __v7m_setup, so setmode can be empty here.
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*/
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.macro setmode, mode, reg
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.endm
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#elif defined(CONFIG_THUMB2_KERNEL)
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.macro setmode, mode, reg
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mov \reg, #\mode
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msr cpsr_c, \reg
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.endm
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#else
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.macro setmode, mode, reg
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msr cpsr_c, #\mode
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.endm
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#endif
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/*
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* Helper macro to enter SVC mode cleanly and mask interrupts. reg is
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* a scratch register for the macro to overwrite.
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*
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* This macro is intended for forcing the CPU into SVC mode at boot time.
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* you cannot return to the original mode.
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*/
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.macro safe_svcmode_maskall reg:req
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#if __LINUX_ARM_ARCH__ >= 6 && !defined(CONFIG_CPU_V7M)
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mrs \reg , cpsr
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eor \reg, \reg, #HYP_MODE
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tst \reg, #MODE_MASK
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bic \reg , \reg , #MODE_MASK
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orr \reg , \reg , #PSR_I_BIT | PSR_F_BIT | SVC_MODE
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THUMB( orr \reg , \reg , #PSR_T_BIT )
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bne 1f
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orr \reg, \reg, #PSR_A_BIT
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badr lr, 2f
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msr spsr_cxsf, \reg
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__MSR_ELR_HYP(14)
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__ERET
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1: msr cpsr_c, \reg
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2:
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#else
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/*
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* workaround for possibly broken pre-v6 hardware
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* (akita, Sharp Zaurus C-1000, PXA270-based)
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*/
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setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, \reg
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#endif
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.endm
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/*
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* STRT/LDRT access macros with ARM and Thumb-2 variants
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*/
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#ifdef CONFIG_THUMB2_KERNEL
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.macro usraccoff, instr, reg, ptr, inc, off, cond, abort, t=TUSER()
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9999:
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.if \inc == 1
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\instr\()b\t\cond\().w \reg, [\ptr, #\off]
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.elseif \inc == 4
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\instr\t\cond\().w \reg, [\ptr, #\off]
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.else
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.error "Unsupported inc macro argument"
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.endif
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.pushsection __ex_table,"a"
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.align 3
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.long 9999b, \abort
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.popsection
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.endm
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.macro usracc, instr, reg, ptr, inc, cond, rept, abort
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@ explicit IT instruction needed because of the label
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@ introduced by the USER macro
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.ifnc \cond,al
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.if \rept == 1
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itt \cond
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.elseif \rept == 2
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ittt \cond
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.else
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.error "Unsupported rept macro argument"
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.endif
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.endif
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@ Slightly optimised to avoid incrementing the pointer twice
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usraccoff \instr, \reg, \ptr, \inc, 0, \cond, \abort
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.if \rept == 2
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usraccoff \instr, \reg, \ptr, \inc, \inc, \cond, \abort
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.endif
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add\cond \ptr, #\rept * \inc
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.endm
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#else /* !CONFIG_THUMB2_KERNEL */
|
|
|
|
.macro usracc, instr, reg, ptr, inc, cond, rept, abort, t=TUSER()
|
|
.rept \rept
|
|
9999:
|
|
.if \inc == 1
|
|
\instr\()b\t\cond \reg, [\ptr], #\inc
|
|
.elseif \inc == 4
|
|
\instr\t\cond \reg, [\ptr], #\inc
|
|
.else
|
|
.error "Unsupported inc macro argument"
|
|
.endif
|
|
|
|
.pushsection __ex_table,"a"
|
|
.align 3
|
|
.long 9999b, \abort
|
|
.popsection
|
|
.endr
|
|
.endm
|
|
|
|
#endif /* CONFIG_THUMB2_KERNEL */
|
|
|
|
.macro strusr, reg, ptr, inc, cond=al, rept=1, abort=9001f
|
|
usracc str, \reg, \ptr, \inc, \cond, \rept, \abort
|
|
.endm
|
|
|
|
.macro ldrusr, reg, ptr, inc, cond=al, rept=1, abort=9001f
|
|
usracc ldr, \reg, \ptr, \inc, \cond, \rept, \abort
|
|
.endm
|
|
|
|
/* Utility macro for declaring string literals */
|
|
.macro string name:req, string
|
|
.type \name , #object
|
|
\name:
|
|
.asciz "\string"
|
|
.size \name , . - \name
|
|
.endm
|
|
|
|
.irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo
|
|
.macro ret\c, reg
|
|
#if __LINUX_ARM_ARCH__ < 6
|
|
mov\c pc, \reg
|
|
#else
|
|
.ifeqs "\reg", "lr"
|
|
bx\c \reg
|
|
.else
|
|
mov\c pc, \reg
|
|
.endif
|
|
#endif
|
|
.endm
|
|
.endr
|
|
|
|
.macro ret.w, reg
|
|
ret \reg
|
|
#ifdef CONFIG_THUMB2_KERNEL
|
|
nop
|
|
#endif
|
|
.endm
|
|
|
|
.macro bug, msg, line
|
|
#ifdef CONFIG_THUMB2_KERNEL
|
|
1: .inst 0xde02
|
|
#else
|
|
1: .inst 0xe7f001f2
|
|
#endif
|
|
#ifdef CONFIG_DEBUG_BUGVERBOSE
|
|
.pushsection .rodata.str, "aMS", %progbits, 1
|
|
2: .asciz "\msg"
|
|
.popsection
|
|
.pushsection __bug_table, "aw"
|
|
.align 2
|
|
.word 1b, 2b
|
|
.hword \line
|
|
.popsection
|
|
#endif
|
|
.endm
|
|
|
|
#ifdef CONFIG_KPROBES
|
|
#define _ASM_NOKPROBE(entry) \
|
|
.pushsection "_kprobe_blacklist", "aw" ; \
|
|
.balign 4 ; \
|
|
.long entry; \
|
|
.popsection
|
|
#else
|
|
#define _ASM_NOKPROBE(entry)
|
|
#endif
|
|
|
|
.macro __adldst_l, op, reg, sym, tmp, c
|
|
.if __LINUX_ARM_ARCH__ < 7
|
|
ldr\c \tmp, .La\@
|
|
.subsection 1
|
|
.align 2
|
|
.La\@: .long \sym - .Lpc\@
|
|
.previous
|
|
.else
|
|
.ifnb \c
|
|
THUMB( ittt \c )
|
|
.endif
|
|
movw\c \tmp, #:lower16:\sym - .Lpc\@
|
|
movt\c \tmp, #:upper16:\sym - .Lpc\@
|
|
.endif
|
|
|
|
#ifndef CONFIG_THUMB2_KERNEL
|
|
.set .Lpc\@, . + 8 // PC bias
|
|
.ifc \op, add
|
|
add\c \reg, \tmp, pc
|
|
.else
|
|
\op\c \reg, [pc, \tmp]
|
|
.endif
|
|
#else
|
|
.Lb\@: add\c \tmp, \tmp, pc
|
|
/*
|
|
* In Thumb-2 builds, the PC bias depends on whether we are currently
|
|
* emitting into a .arm or a .thumb section. The size of the add opcode
|
|
* above will be 2 bytes when emitting in Thumb mode and 4 bytes when
|
|
* emitting in ARM mode, so let's use this to account for the bias.
|
|
*/
|
|
.set .Lpc\@, . + (. - .Lb\@)
|
|
|
|
.ifnc \op, add
|
|
\op\c \reg, [\tmp]
|
|
.endif
|
|
#endif
|
|
.endm
|
|
|
|
/*
|
|
* mov_l - move a constant value or [relocated] address into a register
|
|
*/
|
|
.macro mov_l, dst:req, imm:req, cond
|
|
.if __LINUX_ARM_ARCH__ < 7
|
|
ldr\cond \dst, =\imm
|
|
.else
|
|
movw\cond \dst, #:lower16:\imm
|
|
movt\cond \dst, #:upper16:\imm
|
|
.endif
|
|
.endm
|
|
|
|
/*
|
|
* adr_l - adr pseudo-op with unlimited range
|
|
*
|
|
* @dst: destination register
|
|
* @sym: name of the symbol
|
|
* @cond: conditional opcode suffix
|
|
*/
|
|
.macro adr_l, dst:req, sym:req, cond
|
|
__adldst_l add, \dst, \sym, \dst, \cond
|
|
.endm
|
|
|
|
/*
|
|
* ldr_l - ldr <literal> pseudo-op with unlimited range
|
|
*
|
|
* @dst: destination register
|
|
* @sym: name of the symbol
|
|
* @cond: conditional opcode suffix
|
|
*/
|
|
.macro ldr_l, dst:req, sym:req, cond
|
|
__adldst_l ldr, \dst, \sym, \dst, \cond
|
|
.endm
|
|
|
|
/*
|
|
* str_l - str <literal> pseudo-op with unlimited range
|
|
*
|
|
* @src: source register
|
|
* @sym: name of the symbol
|
|
* @tmp: mandatory scratch register
|
|
* @cond: conditional opcode suffix
|
|
*/
|
|
.macro str_l, src:req, sym:req, tmp:req, cond
|
|
__adldst_l str, \src, \sym, \tmp, \cond
|
|
.endm
|
|
|
|
.macro __ldst_va, op, reg, tmp, sym, cond, offset
|
|
#if __LINUX_ARM_ARCH__ >= 7 || \
|
|
!defined(CONFIG_ARM_HAS_GROUP_RELOCS) || \
|
|
(defined(MODULE) && defined(CONFIG_ARM_MODULE_PLTS))
|
|
mov_l \tmp, \sym, \cond
|
|
#else
|
|
/*
|
|
* Avoid a literal load, by emitting a sequence of ADD/LDR instructions
|
|
* with the appropriate relocations. The combined sequence has a range
|
|
* of -/+ 256 MiB, which should be sufficient for the core kernel and
|
|
* for modules loaded into the module region.
|
|
*/
|
|
.globl \sym
|
|
.reloc .L0_\@, R_ARM_ALU_PC_G0_NC, \sym
|
|
.reloc .L1_\@, R_ARM_ALU_PC_G1_NC, \sym
|
|
.reloc .L2_\@, R_ARM_LDR_PC_G2, \sym
|
|
.L0_\@: sub\cond \tmp, pc, #8 - \offset
|
|
.L1_\@: sub\cond \tmp, \tmp, #4 - \offset
|
|
.L2_\@:
|
|
#endif
|
|
\op\cond \reg, [\tmp, #\offset]
|
|
.endm
|
|
|
|
/*
|
|
* ldr_va - load a 32-bit word from the virtual address of \sym
|
|
*/
|
|
.macro ldr_va, rd:req, sym:req, cond, tmp, offset=0
|
|
.ifnb \tmp
|
|
__ldst_va ldr, \rd, \tmp, \sym, \cond, \offset
|
|
.else
|
|
__ldst_va ldr, \rd, \rd, \sym, \cond, \offset
|
|
.endif
|
|
.endm
|
|
|
|
/*
|
|
* str_va - store a 32-bit word to the virtual address of \sym
|
|
*/
|
|
.macro str_va, rn:req, sym:req, tmp:req, cond
|
|
__ldst_va str, \rn, \tmp, \sym, \cond, 0
|
|
.endm
|
|
|
|
/*
|
|
* ldr_this_cpu_armv6 - Load a 32-bit word from the per-CPU variable 'sym',
|
|
* without using a temp register. Supported in ARM mode
|
|
* only.
|
|
*/
|
|
.macro ldr_this_cpu_armv6, rd:req, sym:req
|
|
this_cpu_offset \rd
|
|
.globl \sym
|
|
.reloc .L0_\@, R_ARM_ALU_PC_G0_NC, \sym
|
|
.reloc .L1_\@, R_ARM_ALU_PC_G1_NC, \sym
|
|
.reloc .L2_\@, R_ARM_LDR_PC_G2, \sym
|
|
add \rd, \rd, pc
|
|
.L0_\@: sub \rd, \rd, #4
|
|
.L1_\@: sub \rd, \rd, #0
|
|
.L2_\@: ldr \rd, [\rd, #4]
|
|
.endm
|
|
|
|
/*
|
|
* ldr_this_cpu - Load a 32-bit word from the per-CPU variable 'sym'
|
|
* into register 'rd', which may be the stack pointer,
|
|
* using 't1' and 't2' as general temp registers. These
|
|
* are permitted to overlap with 'rd' if != sp
|
|
*/
|
|
.macro ldr_this_cpu, rd:req, sym:req, t1:req, t2:req
|
|
#ifndef CONFIG_SMP
|
|
ldr_va \rd, \sym, tmp=\t1
|
|
#elif __LINUX_ARM_ARCH__ >= 7 || \
|
|
!defined(CONFIG_ARM_HAS_GROUP_RELOCS) || \
|
|
(defined(MODULE) && defined(CONFIG_ARM_MODULE_PLTS))
|
|
this_cpu_offset \t1
|
|
mov_l \t2, \sym
|
|
ldr \rd, [\t1, \t2]
|
|
#else
|
|
ldr_this_cpu_armv6 \rd, \sym
|
|
#endif
|
|
.endm
|
|
|
|
/*
|
|
* rev_l - byte-swap a 32-bit value
|
|
*
|
|
* @val: source/destination register
|
|
* @tmp: scratch register
|
|
*/
|
|
.macro rev_l, val:req, tmp:req
|
|
.if __LINUX_ARM_ARCH__ < 6
|
|
eor \tmp, \val, \val, ror #16
|
|
bic \tmp, \tmp, #0x00ff0000
|
|
mov \val, \val, ror #8
|
|
eor \val, \val, \tmp, lsr #8
|
|
.else
|
|
rev \val, \val
|
|
.endif
|
|
.endm
|
|
|
|
.if __LINUX_ARM_ARCH__ < 6
|
|
.set .Lrev_l_uses_tmp, 1
|
|
.else
|
|
.set .Lrev_l_uses_tmp, 0
|
|
.endif
|
|
|
|
/*
|
|
* bl_r - branch and link to register
|
|
*
|
|
* @dst: target to branch to
|
|
* @c: conditional opcode suffix
|
|
*/
|
|
.macro bl_r, dst:req, c
|
|
.if __LINUX_ARM_ARCH__ < 6
|
|
mov\c lr, pc
|
|
mov\c pc, \dst
|
|
.else
|
|
blx\c \dst
|
|
.endif
|
|
.endm
|
|
|
|
#endif /* __ASM_ASSEMBLER_H__ */
|