c00a19c8b1
Floating point half-precision (FPHP) and Advanced SIMD half-precision (ASIMDHP) are VFP features (FEAT_FP16) represented by MVFR1 identification register. These capabilities can optionally exist with VFPv3 and mandatory with VFPv4. Both these new features exist for Armv8 architecture in AArch32 state. These hwcaps may be useful for the userspace to add conditional check before trying to use FEAT_FP16 feature specific instructions. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Amit Daniel Kachhap <amit.kachhap@arm.com> Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
107 lines
3.1 KiB
C
107 lines
3.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* arch/arm/include/asm/vfp.h
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*
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* VFP register definitions.
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* First, the standard VFP set.
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*/
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#ifndef __ASM_VFP_H
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#define __ASM_VFP_H
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#ifndef CONFIG_AS_VFP_VMRS_FPINST
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#define FPSID cr0
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#define FPSCR cr1
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#define MVFR1 cr6
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#define MVFR0 cr7
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#define FPEXC cr8
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#define FPINST cr9
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#define FPINST2 cr10
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#endif
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/* FPSID bits */
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#define FPSID_IMPLEMENTER_BIT (24)
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#define FPSID_IMPLEMENTER_MASK (0xff << FPSID_IMPLEMENTER_BIT)
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#define FPSID_SOFTWARE (1<<23)
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#define FPSID_FORMAT_BIT (21)
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#define FPSID_FORMAT_MASK (0x3 << FPSID_FORMAT_BIT)
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#define FPSID_NODOUBLE (1<<20)
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#define FPSID_ARCH_BIT (16)
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#define FPSID_ARCH_MASK (0xF << FPSID_ARCH_BIT)
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#define FPSID_CPUID_ARCH_MASK (0x7F << FPSID_ARCH_BIT)
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#define FPSID_PART_BIT (8)
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#define FPSID_PART_MASK (0xFF << FPSID_PART_BIT)
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#define FPSID_VARIANT_BIT (4)
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#define FPSID_VARIANT_MASK (0xF << FPSID_VARIANT_BIT)
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#define FPSID_REV_BIT (0)
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#define FPSID_REV_MASK (0xF << FPSID_REV_BIT)
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/* FPEXC bits */
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#define FPEXC_EX (1 << 31)
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#define FPEXC_EN (1 << 30)
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#define FPEXC_DEX (1 << 29)
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#define FPEXC_FP2V (1 << 28)
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#define FPEXC_VV (1 << 27)
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#define FPEXC_TFV (1 << 26)
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#define FPEXC_LENGTH_BIT (8)
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#define FPEXC_LENGTH_MASK (7 << FPEXC_LENGTH_BIT)
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#define FPEXC_IDF (1 << 7)
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#define FPEXC_IXF (1 << 4)
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#define FPEXC_UFF (1 << 3)
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#define FPEXC_OFF (1 << 2)
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#define FPEXC_DZF (1 << 1)
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#define FPEXC_IOF (1 << 0)
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#define FPEXC_TRAP_MASK (FPEXC_IDF|FPEXC_IXF|FPEXC_UFF|FPEXC_OFF|FPEXC_DZF|FPEXC_IOF)
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/* FPSCR bits */
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#define FPSCR_DEFAULT_NAN (1<<25)
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#define FPSCR_FLUSHTOZERO (1<<24)
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#define FPSCR_ROUND_NEAREST (0<<22)
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#define FPSCR_ROUND_PLUSINF (1<<22)
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#define FPSCR_ROUND_MINUSINF (2<<22)
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#define FPSCR_ROUND_TOZERO (3<<22)
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#define FPSCR_RMODE_BIT (22)
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#define FPSCR_RMODE_MASK (3 << FPSCR_RMODE_BIT)
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#define FPSCR_STRIDE_BIT (20)
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#define FPSCR_STRIDE_MASK (3 << FPSCR_STRIDE_BIT)
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#define FPSCR_LENGTH_BIT (16)
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#define FPSCR_LENGTH_MASK (7 << FPSCR_LENGTH_BIT)
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#define FPSCR_IOE (1<<8)
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#define FPSCR_DZE (1<<9)
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#define FPSCR_OFE (1<<10)
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#define FPSCR_UFE (1<<11)
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#define FPSCR_IXE (1<<12)
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#define FPSCR_IDE (1<<15)
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#define FPSCR_IOC (1<<0)
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#define FPSCR_DZC (1<<1)
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#define FPSCR_OFC (1<<2)
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#define FPSCR_UFC (1<<3)
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#define FPSCR_IXC (1<<4)
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#define FPSCR_IDC (1<<7)
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/* MVFR0 bits */
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#define MVFR0_A_SIMD_BIT (0)
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#define MVFR0_A_SIMD_MASK (0xf << MVFR0_A_SIMD_BIT)
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#define MVFR0_SP_BIT (4)
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#define MVFR0_SP_MASK (0xf << MVFR0_SP_BIT)
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#define MVFR0_DP_BIT (8)
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#define MVFR0_DP_MASK (0xf << MVFR0_DP_BIT)
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/* MVFR1 bits */
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#define MVFR1_ASIMDHP_BIT (20)
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#define MVFR1_ASIMDHP_MASK (0xf << MVFR1_ASIMDHP_BIT)
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#define MVFR1_FPHP_BIT (24)
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#define MVFR1_FPHP_MASK (0xf << MVFR1_FPHP_BIT)
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/* Bit patterns for decoding the packaged operation descriptors */
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#define VFPOPDESC_LENGTH_BIT (9)
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#define VFPOPDESC_LENGTH_MASK (0x07 << VFPOPDESC_LENGTH_BIT)
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#define VFPOPDESC_UNUSED_BIT (24)
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#define VFPOPDESC_UNUSED_MASK (0xFF << VFPOPDESC_UNUSED_BIT)
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#define VFPOPDESC_OPDESC_MASK (~(VFPOPDESC_LENGTH_MASK | VFPOPDESC_UNUSED_MASK))
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#ifndef __ASSEMBLY__
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void vfp_disable(void);
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#endif
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#endif /* __ASM_VFP_H */
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