a4bd03e7cb
The arm dts directory has grown to 1559 boards which makes it a bit unwieldy to maintain and use. Past attempts stalled out due to plans to move .dts files out of the kernel tree. Doing that is no longer planned (any time soon at least), so let's go ahead and group .dts files by vendors. This move aligns arm with arm64 .dts file structure. -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEktVUI4SxYhzZyEuo+vtdtY28YcMFAmSTQqAACgkQ+vtdtY28 YcOJtQ/8CUerhXJZTaSCUiOJw7OgPfIU74YZDpByxtHjdKNqL4/khgTBwFxJmeSG QBinBfmXQRUu/vpnCEuODOkILJbe+uUjzBy+cB4a4XR2waVSJSz2tR8U0sN0qqo+ yQ4Sd+ViYIMHmLEfxspBxOYp89Ko/Z+IvOUaZquGnS1X7tTWmlBtQQ5QWDWJ2cwn tJMZ2+b14TOHT3qoJsG5fippxVHIVnjfSxTPRSOlBuuQSnataV/KQUNUYFCxzHhH smM8WZ4RCYMy6pArHpVrGxpI6UvcPuuKQK825B7kWC3YZQ1REU0ub0L1aONeNMAG e9gsmDme4HWUyTNxQ7TjbzMDGGOXvB0I04G/+1MNJBlW6nCcgCqylz/7nUzq5+0j FUAhxZBZtDV6JblKTIT68iV+ibvnbKc5MXZE6FpYRD87d5IQ3yfgAgzCrcPMpZBg kFmOaHFQh4BKjiI4bOVKSXS35XRoCqBA7xDONTV0yJyx4iySZaNYWaUmSunRmtXc lX1w6iDEAwaLfTtCEWMIx6hCZv9CLE3Q2AjehoEqoHOOJ+DC2s+4ianw/iiexQ0J 2LDrXAeU5PDkyODlbc6Wa7O2NwDXfLFK1/roMCITI7ibjADwDpahlrTGFV5GyNNF 3+dWqH6S8RuomIjYRsnt79zmsIMErw+U0qon72peEjBS+FkwHnc= =Jjgv -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmSTSlsACgkQYKtH/8kJ UienLRAArmPvsuwNtx4p/brAgYHRED+c/71dGy3y2c4/m/3Int1t+vNzNT65UfL6 ActweykUwWOP5HHhMkhCY1NyyOSHkMhrSAt7uWpghSPR3iPQ3R8rK+7n3mA2y98l 1Swursyf9tr3PRlmeERkdZbD8Wm4CEtfHKtzt6EwVCYNuCF+oJwjQzr4UFUJB0bj 3keg8rxzNqh1C/ttd2n/1n8eb51+Q4vADof3HC5OfhIjmWrTuhGukjoGdmJ1Ze5E f5bu6YyFNEF7kujiXoT4ZIv9yCQzpTkhFnnUabkXQ50s09CIZ+KM+/OdLm3EP/zy efUvHncfzs56n1IoJGlgQyQ3uzKAjwtwXqKyD+mPC+GIEPDhWmKRAkcoW1L9Box2 pefiSIjTsVwXLM96h7HaUp+KnW0JjSploqMMNcHSmmoSh10Wa38ODHEoYhJJQxqV pu2Dx9AZDaqvkjQaFFYWubpgcs6hL1M0PxzZI1b/cU54BBEOkFcMCCk3jObEAn5H 1gsDsW2KM5fRD0qzlvZIW1I2oHpt52ip+HImsCSRldbXJRBnlofXur1Wn3rorbM5 +5SavKlZ0SE4GYPQXdD1Pi9PHoe9euU5oV5Einz8zZU3HzhUaNp+TqggXDA6jLSz z6nFzX3JJpV6IN7jdYuGwlK3hqncVYVEkQi70SbFGHbgUfiLjIM= =h4ch -----END PGP SIGNATURE----- Merge tag 'arm-dts-mv-for-6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux into soc/dt ARM: dts: Move .dts files to vendor sub-directories The arm dts directory has grown to 1559 boards which makes it a bit unwieldy to maintain and use. Past attempts stalled out due to plans to move .dts files out of the kernel tree. Doing that is no longer planned (any time soon at least), so let's go ahead and group .dts files by vendors. This move aligns arm with arm64 .dts file structure. * tag 'arm-dts-mv-for-6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: ARM: dts: Move .dts files to vendor sub-directories kbuild: Support flat DTBs install ARM: dts: Add .dts files missing from the build ARM: dts: allwinner: Use quoted #include Link: https://lore.kernel.org/r/20230621185025.GA3197738-robh@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
799 lines
23 KiB
Text
799 lines
23 KiB
Text
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* at91sam9n12.dtsi - Device Tree include file for AT91SAM9N12 SoC
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*
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* Copyright (C) 2012 Atmel,
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* 2012 Hong Xu <hong.xu@atmel.com>
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*/
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#include <dt-bindings/dma/at91.h>
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#include <dt-bindings/pinctrl/at91.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/clock/at91.h>
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#include <dt-bindings/mfd/at91-usart.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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model = "Atmel AT91SAM9N12 SoC";
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compatible = "atmel,at91sam9n12";
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interrupt-parent = <&aic>;
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aliases {
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serial0 = &dbgu;
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serial1 = &usart0;
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serial2 = &usart1;
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serial3 = &usart2;
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serial4 = &usart3;
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gpio0 = &pioA;
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gpio1 = &pioB;
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gpio2 = &pioC;
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gpio3 = &pioD;
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tcb0 = &tcb0;
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tcb1 = &tcb1;
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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ssc0 = &ssc0;
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pwm0 = &pwm0;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "arm,arm926ej-s";
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device_type = "cpu";
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reg = <0>;
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};
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};
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memory@20000000 {
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device_type = "memory";
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reg = <0x20000000 0x10000000>;
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};
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clocks {
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slow_xtal: slow_xtal {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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main_xtal: main_xtal {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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};
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sram: sram@300000 {
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compatible = "mmio-sram";
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reg = <0x00300000 0x8000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x00300000 0x8000>;
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};
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ahb {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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apb {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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aic: interrupt-controller@fffff000 {
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#interrupt-cells = <3>;
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compatible = "atmel,at91rm9200-aic";
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interrupt-controller;
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reg = <0xfffff000 0x200>;
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atmel,external-irqs = <31>;
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};
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matrix: matrix@ffffde00 {
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compatible = "atmel,at91sam9n12-matrix", "syscon";
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reg = <0xffffde00 0x100>;
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};
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pmecc: ecc-engine@ffffe000 {
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compatible = "atmel,at91sam9g45-pmecc";
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reg = <0xffffe000 0x600>,
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<0xffffe600 0x200>;
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};
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ramc0: ramc@ffffe800 {
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compatible = "atmel,at91sam9g45-ddramc";
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reg = <0xffffe800 0x200>;
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clocks = <&pmc PMC_TYPE_SYSTEM 2>;
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clock-names = "ddrck";
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};
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smc: smc@ffffea00 {
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compatible = "atmel,at91sam9260-smc", "syscon";
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reg = <0xffffea00 0x200>;
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};
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pmc: clock-controller@fffffc00 {
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compatible = "atmel,at91sam9n12-pmc", "syscon";
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reg = <0xfffffc00 0x200>;
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#clock-cells = <2>;
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clocks = <&clk32k>, <&main_xtal>;
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clock-names = "slow_clk", "main_xtal";
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interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
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};
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reset-controller@fffffe00 {
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compatible = "atmel,at91sam9g45-rstc";
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reg = <0xfffffe00 0x10>;
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clocks = <&clk32k>;
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};
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pit: timer@fffffe30 {
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compatible = "atmel,at91sam9260-pit";
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reg = <0xfffffe30 0xf>;
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interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
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clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
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};
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poweroff@fffffe10 {
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compatible = "atmel,at91sam9x5-shdwc";
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reg = <0xfffffe10 0x10>;
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clocks = <&clk32k>;
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};
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clk32k: clock-controller@fffffe50 {
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compatible = "atmel,at91sam9x5-sckc";
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reg = <0xfffffe50 0x4>;
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clocks = <&slow_xtal>;
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#clock-cells = <0>;
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};
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mmc0: mmc@f0008000 {
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compatible = "atmel,hsmci";
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reg = <0xf0008000 0x600>;
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interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
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dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>;
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dma-names = "rxtx";
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clocks = <&pmc PMC_TYPE_PERIPHERAL 12>;
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clock-names = "mci_clk";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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tcb0: timer@f8008000 {
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compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xf8008000 0x100>;
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interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k>;
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clock-names = "t0_clk", "slow_clk";
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};
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tcb1: timer@f800c000 {
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compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xf800c000 0x100>;
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interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k>;
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clock-names = "t0_clk", "slow_clk";
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};
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hlcdc: hlcdc@f8038000 {
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compatible = "atmel,at91sam9n12-hlcdc";
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reg = <0xf8038000 0x2000>;
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interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 25>, <&pmc PMC_TYPE_SYSTEM 3>, <&clk32k>;
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clock-names = "periph_clk", "sys_clk", "slow_clk";
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status = "disabled";
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hlcdc-display-controller {
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compatible = "atmel,hlcdc-display-controller";
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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};
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};
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hlcdc_pwm: hlcdc-pwm {
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compatible = "atmel,hlcdc-pwm";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lcd_pwm>;
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#pwm-cells = <3>;
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};
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};
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dma: dma-controller@ffffec00 {
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compatible = "atmel,at91sam9g45-dma";
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reg = <0xffffec00 0x200>;
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interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
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#dma-cells = <2>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
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clock-names = "dma_clk";
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};
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pinctrl@fffff400 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
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ranges = <0xfffff400 0xfffff400 0x800>;
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atmel,mux-mask = <
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/* A B C */
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0xffffffff 0xffe07983 0x00000000 /* pioA */
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0x00040000 0x00047e0f 0x00000000 /* pioB */
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0xfdffffff 0x07c00000 0xb83fffff /* pioC */
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0x003fffff 0x003f8000 0x00000000 /* pioD */
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>;
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/* shared pinctrl settings */
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dbgu {
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pinctrl_dbgu: dbgu-0 {
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atmel,pins =
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<AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
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AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
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};
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};
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lcd {
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pinctrl_lcd_base: lcd-base-0 {
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atmel,pins =
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<AT91_PIOC 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDVSYNC */
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AT91_PIOC 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDHSYNC */
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AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDDISP */
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AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDDEN */
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AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPCK */
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};
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pinctrl_lcd_pwm: lcd-pwm-0 {
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atmel,pins = <AT91_PIOC 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPWM */
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};
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pinctrl_lcd_rgb888: lcd-rgb-3 {
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atmel,pins =
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<AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
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AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
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AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
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AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
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AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
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AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
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AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
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AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
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AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
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AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
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AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
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AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */
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AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */
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AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */
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AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */
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AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */
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AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD16 pin */
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AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD17 pin */
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AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD18 pin */
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AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD19 pin */
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AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD20 pin */
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AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD21 pin */
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AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD22 pin */
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AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */
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};
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};
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usart0 {
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pinctrl_usart0: usart0-0 {
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atmel,pins =
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<AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA1 periph A with pullup */
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AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA0 periph A */
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};
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pinctrl_usart0_rts: usart0_rts-0 {
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atmel,pins =
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<AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA2 periph A */
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};
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pinctrl_usart0_cts: usart0_cts-0 {
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atmel,pins =
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<AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA3 periph A */
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};
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};
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usart1 {
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pinctrl_usart1: usart1-0 {
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atmel,pins =
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<AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA6 periph A with pullup */
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AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA5 periph A */
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};
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};
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usart2 {
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pinctrl_usart2: usart2-0 {
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atmel,pins =
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<AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA8 periph A with pullup */
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AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA7 periph A */
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};
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pinctrl_usart2_rts: usart2_rts-0 {
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atmel,pins =
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<AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB0 periph B */
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};
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pinctrl_usart2_cts: usart2_cts-0 {
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atmel,pins =
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<AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB1 periph B */
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};
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};
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usart3 {
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pinctrl_usart3: usart3-0 {
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atmel,pins =
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<AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PC23 periph B with pullup */
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AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC22 periph B */
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};
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pinctrl_usart3_rts: usart3_rts-0 {
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atmel,pins =
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<AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC24 periph B */
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};
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pinctrl_usart3_cts: usart3_cts-0 {
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atmel,pins =
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<AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC25 periph B */
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};
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};
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uart0 {
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pinctrl_uart0: uart0-0 {
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atmel,pins =
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<AT91_PIOC 9 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* PC9 periph C with pullup */
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AT91_PIOC 8 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC8 periph C */
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};
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};
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uart1 {
|
|
pinctrl_uart1: uart1-0 {
|
|
atmel,pins =
|
|
<AT91_PIOC 16 AT91_PERIPH_C AT91_PINCTRL_NONE
|
|
AT91_PIOC 17 AT91_PERIPH_C AT91_PINCTRL_PULL_UP>;
|
|
};
|
|
};
|
|
|
|
nand {
|
|
pinctrl_nand_rb: nand-rb-0 {
|
|
atmel,pins =
|
|
<AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
|
|
};
|
|
|
|
pinctrl_nand_cs: nand-cs-0 {
|
|
atmel,pins =
|
|
<AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
|
|
};
|
|
};
|
|
|
|
mmc0 {
|
|
pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
|
|
atmel,pins =
|
|
<AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */
|
|
AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA16 periph A with pullup */
|
|
AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA15 periph A with pullup */
|
|
};
|
|
|
|
pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
|
|
atmel,pins =
|
|
<AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA18 periph A with pullup */
|
|
AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA19 periph A with pullup */
|
|
AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA20 periph A with pullup */
|
|
};
|
|
|
|
pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 {
|
|
atmel,pins =
|
|
<AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA11 periph B with pullup */
|
|
AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA12 periph B with pullup */
|
|
AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA13 periph B with pullup */
|
|
AT91_PIOA 14 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA14 periph B with pullup */
|
|
};
|
|
};
|
|
|
|
ssc0 {
|
|
pinctrl_ssc0_tx: ssc0_tx-0 {
|
|
atmel,pins =
|
|
<AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA24 periph B */
|
|
AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA25 periph B */
|
|
AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA26 periph B */
|
|
};
|
|
|
|
pinctrl_ssc0_rx: ssc0_rx-0 {
|
|
atmel,pins =
|
|
<AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */
|
|
AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */
|
|
AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA29 periph B */
|
|
};
|
|
};
|
|
|
|
spi0 {
|
|
pinctrl_spi0: spi0-0 {
|
|
atmel,pins =
|
|
<AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A SPI0_MISO pin */
|
|
AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A SPI0_MOSI pin */
|
|
AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA13 periph A SPI0_SPCK pin */
|
|
};
|
|
};
|
|
|
|
spi1 {
|
|
pinctrl_spi1: spi1-0 {
|
|
atmel,pins =
|
|
<AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA21 periph B SPI1_MISO pin */
|
|
AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA22 periph B SPI1_MOSI pin */
|
|
AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA23 periph B SPI1_SPCK pin */
|
|
};
|
|
};
|
|
|
|
i2c0 {
|
|
pinctrl_i2c0: i2c0-0 {
|
|
atmel,pins =
|
|
<AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE
|
|
AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
|
};
|
|
};
|
|
|
|
i2c1 {
|
|
pinctrl_i2c1: i2c1-0 {
|
|
atmel,pins =
|
|
<AT91_PIOC 0 AT91_PERIPH_C AT91_PINCTRL_NONE
|
|
AT91_PIOC 1 AT91_PERIPH_C AT91_PINCTRL_NONE>;
|
|
};
|
|
};
|
|
|
|
tcb0 {
|
|
pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
|
|
atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
|
};
|
|
|
|
pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
|
|
atmel,pins = <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
|
};
|
|
|
|
pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
|
|
atmel,pins = <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
|
};
|
|
|
|
pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
|
|
atmel,pins = <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
|
};
|
|
|
|
pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
|
|
atmel,pins = <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
|
};
|
|
|
|
pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
|
|
atmel,pins = <AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
|
};
|
|
|
|
pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
|
|
atmel,pins = <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
|
};
|
|
|
|
pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
|
|
atmel,pins = <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
|
};
|
|
|
|
pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
|
|
atmel,pins = <AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
|
};
|
|
};
|
|
|
|
tcb1 {
|
|
pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
|
|
atmel,pins = <AT91_PIOC 4 AT91_PERIPH_C AT91_PINCTRL_NONE>;
|
|
};
|
|
|
|
pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
|
|
atmel,pins = <AT91_PIOC 7 AT91_PERIPH_C AT91_PINCTRL_NONE>;
|
|
};
|
|
|
|
pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
|
|
atmel,pins = <AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE>;
|
|
};
|
|
|
|
pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
|
|
atmel,pins = <AT91_PIOC 2 AT91_PERIPH_C AT91_PINCTRL_NONE>;
|
|
};
|
|
|
|
pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
|
|
atmel,pins = <AT91_PIOC 5 AT91_PERIPH_C AT91_PINCTRL_NONE>;
|
|
};
|
|
|
|
pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
|
|
atmel,pins = <AT91_PIOC 12 AT91_PERIPH_C AT91_PINCTRL_NONE>;
|
|
};
|
|
|
|
pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
|
|
atmel,pins = <AT91_PIOC 3 AT91_PERIPH_C AT91_PINCTRL_NONE>;
|
|
};
|
|
|
|
pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
|
|
atmel,pins = <AT91_PIOC 6 AT91_PERIPH_C AT91_PINCTRL_NONE>;
|
|
};
|
|
|
|
pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
|
|
atmel,pins = <AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE>;
|
|
};
|
|
};
|
|
|
|
pioA: gpio@fffff400 {
|
|
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
|
|
reg = <0xfffff400 0x200>;
|
|
interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
|
|
#gpio-cells = <2>;
|
|
gpio-controller;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
|
|
};
|
|
|
|
pioB: gpio@fffff600 {
|
|
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
|
|
reg = <0xfffff600 0x200>;
|
|
interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
|
|
#gpio-cells = <2>;
|
|
gpio-controller;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
|
|
};
|
|
|
|
pioC: gpio@fffff800 {
|
|
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
|
|
reg = <0xfffff800 0x200>;
|
|
interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
|
|
#gpio-cells = <2>;
|
|
gpio-controller;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 3>;
|
|
};
|
|
|
|
pioD: gpio@fffffa00 {
|
|
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
|
|
reg = <0xfffffa00 0x200>;
|
|
interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
|
|
#gpio-cells = <2>;
|
|
gpio-controller;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 3>;
|
|
};
|
|
};
|
|
|
|
dbgu: serial@fffff200 {
|
|
compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
|
|
reg = <0xfffff200 0x200>;
|
|
atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
|
|
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_dbgu>;
|
|
clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
|
|
clock-names = "usart";
|
|
status = "disabled";
|
|
};
|
|
|
|
ssc0: ssc@f0010000 {
|
|
compatible = "atmel,at91sam9g45-ssc";
|
|
reg = <0xf0010000 0x4000>;
|
|
interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
|
|
dmas = <&dma 0 AT91_DMA_CFG_PER_ID(21)>,
|
|
<&dma 0 AT91_DMA_CFG_PER_ID(22)>;
|
|
dma-names = "tx", "rx";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 28>;
|
|
clock-names = "pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
usart0: serial@f801c000 {
|
|
compatible = "atmel,at91sam9260-usart";
|
|
reg = <0xf801c000 0x4000>;
|
|
atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
|
|
interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_usart0>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
|
|
clock-names = "usart";
|
|
status = "disabled";
|
|
};
|
|
|
|
usart1: serial@f8020000 {
|
|
compatible = "atmel,at91sam9260-usart";
|
|
reg = <0xf8020000 0x4000>;
|
|
atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
|
|
interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_usart1>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
|
|
clock-names = "usart";
|
|
status = "disabled";
|
|
};
|
|
|
|
usart2: serial@f8024000 {
|
|
compatible = "atmel,at91sam9260-usart";
|
|
reg = <0xf8024000 0x4000>;
|
|
atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
|
|
interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_usart2>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
|
|
clock-names = "usart";
|
|
status = "disabled";
|
|
};
|
|
|
|
usart3: serial@f8028000 {
|
|
compatible = "atmel,at91sam9260-usart";
|
|
reg = <0xf8028000 0x4000>;
|
|
atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
|
|
interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_usart3>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
|
|
clock-names = "usart";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c0: i2c@f8010000 {
|
|
compatible = "atmel,at91sam9x5-i2c";
|
|
reg = <0xf8010000 0x100>;
|
|
interrupts = <9 IRQ_TYPE_LEVEL_HIGH 6>;
|
|
dmas = <&dma 1 AT91_DMA_CFG_PER_ID(13)>,
|
|
<&dma 1 AT91_DMA_CFG_PER_ID(14)>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_i2c0>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c1: i2c@f8014000 {
|
|
compatible = "atmel,at91sam9x5-i2c";
|
|
reg = <0xf8014000 0x100>;
|
|
interrupts = <10 IRQ_TYPE_LEVEL_HIGH 6>;
|
|
dmas = <&dma 1 AT91_DMA_CFG_PER_ID(15)>,
|
|
<&dma 1 AT91_DMA_CFG_PER_ID(16)>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_i2c1>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi0: spi@f0000000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "atmel,at91rm9200-spi";
|
|
reg = <0xf0000000 0x100>;
|
|
interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
|
|
dmas = <&dma 1 AT91_DMA_CFG_PER_ID(1)>,
|
|
<&dma 1 AT91_DMA_CFG_PER_ID(2)>;
|
|
dma-names = "tx", "rx";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_spi0>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
|
|
clock-names = "spi_clk";
|
|
status = "disabled";
|
|
};
|
|
|
|
spi1: spi@f0004000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "atmel,at91rm9200-spi";
|
|
reg = <0xf0004000 0x100>;
|
|
interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>;
|
|
dmas = <&dma 1 AT91_DMA_CFG_PER_ID(3)>,
|
|
<&dma 1 AT91_DMA_CFG_PER_ID(4)>;
|
|
dma-names = "tx", "rx";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_spi1>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
|
|
clock-names = "spi_clk";
|
|
status = "disabled";
|
|
};
|
|
|
|
watchdog@fffffe40 {
|
|
compatible = "atmel,at91sam9260-wdt";
|
|
reg = <0xfffffe40 0x10>;
|
|
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
clocks = <&clk32k>;
|
|
atmel,watchdog-type = "hardware";
|
|
atmel,reset-type = "all";
|
|
atmel,dbg-halt;
|
|
status = "disabled";
|
|
};
|
|
|
|
rtc@fffffeb0 {
|
|
compatible = "atmel,at91rm9200-rtc";
|
|
reg = <0xfffffeb0 0x40>;
|
|
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
clocks = <&clk32k>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm0: pwm@f8034000 {
|
|
compatible = "atmel,at91sam9rl-pwm";
|
|
reg = <0xf8034000 0x300>;
|
|
interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>;
|
|
#pwm-cells = <3>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 18>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usb1: gadget@f803c000 {
|
|
compatible = "atmel,at91sam9260-udc";
|
|
reg = <0xf803c000 0x4000>;
|
|
interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_SYSTEM 7>;
|
|
clock-names = "pclk", "hclk";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
usb0: ohci@500000 {
|
|
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
|
|
reg = <0x00500000 0x00100000>;
|
|
interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_SYSTEM 6>;
|
|
clock-names = "ohci_clk", "hclk", "uhpck";
|
|
status = "disabled";
|
|
};
|
|
|
|
ebi: ebi@10000000 {
|
|
compatible = "atmel,at91sam9x5-ebi";
|
|
#address-cells = <2>;
|
|
#size-cells = <1>;
|
|
atmel,smc = <&smc>;
|
|
atmel,matrix = <&matrix>;
|
|
reg = <0x10000000 0x60000000>;
|
|
ranges = <0x0 0x0 0x10000000 0x10000000
|
|
0x1 0x0 0x20000000 0x10000000
|
|
0x2 0x0 0x30000000 0x10000000
|
|
0x3 0x0 0x40000000 0x10000000
|
|
0x4 0x0 0x50000000 0x10000000
|
|
0x5 0x0 0x60000000 0x10000000>;
|
|
clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
|
|
status = "disabled";
|
|
|
|
nand_controller: nand-controller {
|
|
compatible = "atmel,at91sam9g45-nand-controller";
|
|
ecc-engine = <&pmecc>;
|
|
#address-cells = <2>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|
|
|
|
i2c-gpio-0 {
|
|
compatible = "i2c-gpio";
|
|
gpios = <&pioA 30 GPIO_ACTIVE_HIGH /* sda */
|
|
&pioA 31 GPIO_ACTIVE_HIGH /* scl */
|
|
>;
|
|
i2c-gpio,sda-open-drain;
|
|
i2c-gpio,scl-open-drain;
|
|
i2c-gpio,delay-us = <2>; /* ~100 kHz */
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
};
|