724ba67515
The arm dts directory has grown to 1559 boards which makes it a bit unwieldy to maintain and use. Past attempts stalled out due to plans to move .dts files out of the kernel tree. Doing that is no longer planned (any time soon at least), so let's go ahead and group .dts files by vendors. This move aligns arm with arm64 .dts file structure. There's no change to dtbs_install as the flat structure is maintained on install. The naming of vendor directories is roughly in this order of preference: - Matching original and current SoC vendor prefix/name (e.g. ti, qcom) - Current vendor prefix/name if still actively sold (SoCs which have been aquired) (e.g. nxp/imx) - Existing platform name for older platforms not sold/maintained by any company (e.g. gemini, nspire) The whole move was scripted with the exception of MAINTAINERS and a few makefile fixups. Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Michal Simek <michal.simek@amd.com> #Xilinx Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Neil Armstrong <neil.armstrong@linaro.org> Acked-by: Paul Barker <paul.barker@sancloud.com> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Wei Xu <xuwei5@hisilicon.com> #hisilicon Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Nick Hawkins <nick.hawkins@hpe.com> Acked-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Acked-by: Peter Rosin <peda@axentia.se> Acked-by: Jesper Nilsson <jesper.nilsson@axis.com> Acked-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> #broadcom Acked-by: Manivannan Sadhasivam <mani@kernel.org> Reviewed-by: Jisheng Zhang <jszhang@kernel.org> Acked-by: Patrice Chotard <patrice.chotard@foss.st.com> Acked-by: Romain Perier <romain.perier@gmail.com> Acked-by: Alexandre TORGUE <alexandre.torgue@st.com> Acked-by: Shawn Guo <shawnguo@kernel.org> Acked-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Acked-by: Enric Balletbo i Serra <eballetbo@gmail.com> Signed-off-by: Rob Herring <robh@kernel.org>
99 lines
2.2 KiB
Text
99 lines
2.2 KiB
Text
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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/*
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* Copyright (C) 2023 DH electronics GmbH
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*
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* DHCOM iMX6ULL variant:
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* DHCM-iMX6ULL-C080-R051-F0409-SPI-E2-CAN2-SD-RTC-ADC-I-01D2
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* DHCOR PCB number: 578-200 or newer
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* DHCOM PCB number: 579-200 or newer
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* DRC02 PCB number: 568-100 or newer (2nd ethernet by SoM)
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*/
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/dts-v1/;
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#include "imx6ull-dhcom-som.dtsi"
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#include "imx6ull-dhcom-som-cfg-sdcard.dtsi"
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/ {
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model = "DH electronics i.MX6ULL DHCOM on DRC02";
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compatible = "dh,imx6ull-dhcom-drc02", "dh,imx6ull-dhcom-som",
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"dh,imx6ull-dhcor-som", "fsl,imx6ull";
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};
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/*
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* The signals for CAN2 TX and RX are routed to the DHCOM UART1 RTS/CTS pins.
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* Therefore the UART RTS/CTS must be output on other DHCOM pins, see uart1
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* node below.
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*/
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&can2 {
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status = "okay";
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};
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&gpio1 {
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gpio-line-names =
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"", "", "", "",
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"", "", "", "",
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"", "", "", "DRC02-In2",
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"", "", "", "",
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"", "", "DHCOM-I", "",
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"", "", "", "",
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"", "", "", "",
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"", "", "", "";
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};
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&gpio4 {
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gpio-line-names =
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"", "", "", "",
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"", "", "", "",
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"", "", "", "",
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"", "", "", "",
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"", "DRC02-HW0", "DRC02-HW1", "DHCOM-M",
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"DRC02-HW2", "DHCOM-U", "DHCOM-T", "DHCOM-S",
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"DHCOM-R", "DHCOM-Q", "DHCOM-P", "DHCOM-O",
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"DHCOM-N", "", "", "";
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/*
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* NOTE: On DRC02, the RS485_RX_En is controlled by a separate
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* GPIO line, however the i.MX6ULL UART driver assumes RX happens
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* during TX anyway and that it only controls drive enable DE
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* line. Hence, the RX is always enabled here.
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*/
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rs485-rx-en-hog {
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gpio-hog;
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gpios = <25 0>; /* GPIO Q */
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line-name = "rs485-rx-en";
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output-low;
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};
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};
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&gpio5 {
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gpio-line-names =
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"DHCOM-A", "DHCOM-B", "DHCOM-C", "DRC02-Out2",
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"DHCOM-E", "", "", "DRC02-Out1",
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"DRC02-In1", "DHCOM-H", "", "",
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"", "", "", "",
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"", "", "", "",
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"", "", "", "",
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"", "", "", "",
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"", "", "", "";
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};
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/* DHCOM I2C2 */
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&i2c1 {
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eeprom@56 {
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compatible = "atmel,24c04";
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reg = <0x56>;
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pagesize = <16>;
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};
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};
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&uart1 {
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/delete-property/ uart-has-rtscts;
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rts-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; /* GPIO I */
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cts-gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>; /* GPIO M */
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};
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/* Use UART as RS485 */
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&uart2 {
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/delete-property/ uart-has-rtscts;
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linux,rs485-enabled-at-boot-time;
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rts-gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; /* GPIO P */
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};
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