724ba67515
The arm dts directory has grown to 1559 boards which makes it a bit unwieldy to maintain and use. Past attempts stalled out due to plans to move .dts files out of the kernel tree. Doing that is no longer planned (any time soon at least), so let's go ahead and group .dts files by vendors. This move aligns arm with arm64 .dts file structure. There's no change to dtbs_install as the flat structure is maintained on install. The naming of vendor directories is roughly in this order of preference: - Matching original and current SoC vendor prefix/name (e.g. ti, qcom) - Current vendor prefix/name if still actively sold (SoCs which have been aquired) (e.g. nxp/imx) - Existing platform name for older platforms not sold/maintained by any company (e.g. gemini, nspire) The whole move was scripted with the exception of MAINTAINERS and a few makefile fixups. Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Michal Simek <michal.simek@amd.com> #Xilinx Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Neil Armstrong <neil.armstrong@linaro.org> Acked-by: Paul Barker <paul.barker@sancloud.com> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Wei Xu <xuwei5@hisilicon.com> #hisilicon Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Nick Hawkins <nick.hawkins@hpe.com> Acked-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Acked-by: Peter Rosin <peda@axentia.se> Acked-by: Jesper Nilsson <jesper.nilsson@axis.com> Acked-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> #broadcom Acked-by: Manivannan Sadhasivam <mani@kernel.org> Reviewed-by: Jisheng Zhang <jszhang@kernel.org> Acked-by: Patrice Chotard <patrice.chotard@foss.st.com> Acked-by: Romain Perier <romain.perier@gmail.com> Acked-by: Alexandre TORGUE <alexandre.torgue@st.com> Acked-by: Shawn Guo <shawnguo@kernel.org> Acked-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Acked-by: Enric Balletbo i Serra <eballetbo@gmail.com> Signed-off-by: Rob Herring <robh@kernel.org>
294 lines
6.8 KiB
Text
294 lines
6.8 KiB
Text
/*
|
|
* Support for CompuLab CL-SOM-iMX7 System-on-Module
|
|
*
|
|
* Copyright (C) 2015 CompuLab Ltd. - http://www.compulab.co.il/
|
|
* Author: Ilya Ledvich <ilya@compulab.co.il>
|
|
*
|
|
* This file is dual-licensed: you can use it either under the terms
|
|
* of the GPL or the X11 license, at your option. Note that this dual
|
|
* licensing only applies to this file, and not this project as a
|
|
* whole.
|
|
*/
|
|
|
|
/dts-v1/;
|
|
|
|
#include "imx7d.dtsi"
|
|
|
|
/ {
|
|
model = "CompuLab CL-SOM-iMX7";
|
|
compatible = "compulab,cl-som-imx7", "fsl,imx7d";
|
|
|
|
memory@80000000 {
|
|
device_type = "memory";
|
|
reg = <0x80000000 0x10000000>; /* 256 MB - minimal configuration */
|
|
};
|
|
|
|
reg_usb_otg1_vbus: regulator-vbus {
|
|
compatible = "regulator-fixed";
|
|
regulator-name = "usb_otg1_vbus";
|
|
regulator-min-microvolt = <5000000>;
|
|
regulator-max-microvolt = <5000000>;
|
|
gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
|
|
enable-active-high;
|
|
};
|
|
};
|
|
|
|
&cpu0 {
|
|
cpu-supply = <&sw1a_reg>;
|
|
};
|
|
|
|
&cpu1 {
|
|
cpu-supply = <&sw1a_reg>;
|
|
};
|
|
|
|
&fec1 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_enet1>;
|
|
assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
|
|
<&clks IMX7D_ENET1_TIME_ROOT_CLK>;
|
|
assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
|
|
assigned-clock-rates = <0>, <100000000>;
|
|
phy-mode = "rgmii-id";
|
|
phy-handle = <ðphy0>;
|
|
fsl,magic-packet;
|
|
status = "okay";
|
|
|
|
mdio {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
ethphy0: ethernet-phy@0 {
|
|
compatible = "ethernet-phy-ieee802.3-c22";
|
|
reg = <0>;
|
|
};
|
|
|
|
ethphy1: ethernet-phy@1 {
|
|
compatible = "ethernet-phy-ieee802.3-c22";
|
|
reg = <1>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&fec2 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_enet2>;
|
|
assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
|
|
<&clks IMX7D_ENET2_TIME_ROOT_CLK>;
|
|
assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
|
|
assigned-clock-rates = <0>, <100000000>;
|
|
phy-mode = "rgmii-id";
|
|
phy-handle = <ðphy1>;
|
|
fsl,magic-packet;
|
|
status = "okay";
|
|
};
|
|
|
|
&i2c2 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_i2c2>;
|
|
status = "okay";
|
|
|
|
pmic: pmic@8 {
|
|
compatible = "fsl,pfuze3000";
|
|
reg = <0x8>;
|
|
|
|
regulators {
|
|
sw1a_reg: sw1a {
|
|
regulator-min-microvolt = <700000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
regulator-ramp-delay = <6250>;
|
|
};
|
|
|
|
/* use sw1c_reg to align with pfuze100/pfuze200 */
|
|
sw1c_reg: sw1b {
|
|
regulator-min-microvolt = <700000>;
|
|
regulator-max-microvolt = <1475000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
regulator-ramp-delay = <6250>;
|
|
};
|
|
|
|
sw2_reg: sw2 {
|
|
regulator-min-microvolt = <1500000>;
|
|
regulator-max-microvolt = <1850000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
};
|
|
|
|
sw3a_reg: sw3 {
|
|
regulator-min-microvolt = <900000>;
|
|
regulator-max-microvolt = <1650000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
};
|
|
|
|
swbst_reg: swbst {
|
|
regulator-min-microvolt = <5000000>;
|
|
regulator-max-microvolt = <5150000>;
|
|
};
|
|
|
|
snvs_reg: vsnvs {
|
|
regulator-min-microvolt = <1000000>;
|
|
regulator-max-microvolt = <3000000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
};
|
|
|
|
vref_reg: vrefddr {
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
};
|
|
|
|
vgen1_reg: vldo1 {
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
regulator-always-on;
|
|
};
|
|
|
|
vgen2_reg: vldo2 {
|
|
regulator-min-microvolt = <800000>;
|
|
regulator-max-microvolt = <1550000>;
|
|
};
|
|
|
|
vgen3_reg: vccsd {
|
|
regulator-min-microvolt = <2850000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
regulator-always-on;
|
|
};
|
|
|
|
vgen4_reg: v33 {
|
|
regulator-min-microvolt = <2850000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
regulator-always-on;
|
|
};
|
|
|
|
vgen5_reg: vldo3 {
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
regulator-always-on;
|
|
};
|
|
|
|
vgen6_reg: vldo4 {
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
regulator-always-on;
|
|
};
|
|
};
|
|
};
|
|
|
|
pca9555: pca9555@20 {
|
|
compatible = "nxp,pca9555";
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
reg = <0x20>;
|
|
};
|
|
|
|
eeprom@50 {
|
|
compatible = "atmel,24c08";
|
|
reg = <0x50>;
|
|
pagesize = <16>;
|
|
};
|
|
};
|
|
|
|
&uart1 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_uart1>;
|
|
assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
|
|
assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
|
|
status = "okay";
|
|
};
|
|
|
|
&usbotg1 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_usbotg1>;
|
|
vbus-supply = <®_usb_otg1_vbus>;
|
|
status = "okay";
|
|
};
|
|
|
|
&usdhc3 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_usdhc3>;
|
|
assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
|
|
assigned-clock-rates = <400000000>;
|
|
bus-width = <8>;
|
|
fsl,tuning-step = <2>;
|
|
non-removable;
|
|
status = "okay";
|
|
};
|
|
|
|
&iomuxc {
|
|
pinctrl_enet1: enet1grp {
|
|
fsl,pins = <
|
|
MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x30
|
|
MX7D_PAD_SD2_WP__ENET1_MDC 0x30
|
|
MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x11
|
|
MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x11
|
|
MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x11
|
|
MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x11
|
|
MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x11
|
|
MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x11
|
|
MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x11
|
|
MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x11
|
|
MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x11
|
|
MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x11
|
|
MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x11
|
|
MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x11
|
|
>;
|
|
};
|
|
|
|
pinctrl_enet2: enet2grp {
|
|
fsl,pins = <
|
|
MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x11
|
|
MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x11
|
|
MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x11
|
|
MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x11
|
|
MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x11
|
|
MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x11
|
|
MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x11
|
|
MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x11
|
|
MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x11
|
|
MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x11
|
|
MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x11
|
|
MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x11
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c2: i2c2grp {
|
|
fsl,pins = <
|
|
MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f
|
|
MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart1: uart1grp {
|
|
fsl,pins = <
|
|
MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79
|
|
MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc3: usdhc3grp {
|
|
fsl,pins = <
|
|
MX7D_PAD_SD3_CMD__SD3_CMD 0x59
|
|
MX7D_PAD_SD3_CLK__SD3_CLK 0x19
|
|
MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
|
|
MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
|
|
MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
|
|
MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
|
|
MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
|
|
MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
|
|
MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
|
|
MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
|
|
MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19
|
|
>;
|
|
};
|
|
};
|
|
|
|
&iomuxc_lpsr {
|
|
pinctrl_usbotg1: usbotg1grp {
|
|
fsl,pins = <
|
|
MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x14 /* OTG PWREN */
|
|
>;
|
|
};
|
|
};
|