c7368ddba2
When I compiled the following code for ARM, I encountered numerous
errors.
[Test Code]
#include <linux/compiler.h>
#include <linux/uaccess.h>
int foo(int *x, int __user *ptr)
{
return get_user(*x, ptr);
}
To fix the errors, make some asm headers self-contained:
1. In arch/arm/include/asm/domain.h, include <linux/thread_info.h>
for current_thread_info().
2. In arch/arm/include/asm/traps.h, remove unneeded __init, and
include <linux/linkage.h> for asmlinkage.
3. In arch/arm/include/asm/uaccess.h, include <linux/kernel.h> for
might_fault().
Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
141 lines
3.3 KiB
C
141 lines
3.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* arch/arm/include/asm/domain.h
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*
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* Copyright (C) 1999 Russell King.
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*/
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#ifndef __ASM_PROC_DOMAIN_H
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#define __ASM_PROC_DOMAIN_H
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#ifndef __ASSEMBLY__
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#include <linux/thread_info.h>
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#include <asm/barrier.h>
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#endif
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/*
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* Domain numbers
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*
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* DOMAIN_IO - domain 2 includes all IO only
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* DOMAIN_USER - domain 1 includes all user memory only
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* DOMAIN_KERNEL - domain 0 includes all kernel memory only
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*
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* The domain numbering depends on whether we support 36 physical
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* address for I/O or not. Addresses above the 32 bit boundary can
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* only be mapped using supersections and supersections can only
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* be set for domain 0. We could just default to DOMAIN_IO as zero,
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* but there may be systems with supersection support and no 36-bit
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* addressing. In such cases, we want to map system memory with
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* supersections to reduce TLB misses and footprint.
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*
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* 36-bit addressing and supersections are only available on
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* CPUs based on ARMv6+ or the Intel XSC3 core.
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*/
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#ifndef CONFIG_IO_36
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#define DOMAIN_KERNEL 0
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#define DOMAIN_USER 1
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#define DOMAIN_IO 2
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#else
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#define DOMAIN_KERNEL 2
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#define DOMAIN_USER 1
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#define DOMAIN_IO 0
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#endif
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#define DOMAIN_VECTORS 3
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/*
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* Domain types
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*/
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#define DOMAIN_NOACCESS 0
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#define DOMAIN_CLIENT 1
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#ifdef CONFIG_CPU_USE_DOMAINS
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#define DOMAIN_MANAGER 3
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#else
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#define DOMAIN_MANAGER 1
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#endif
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#define domain_mask(dom) ((3) << (2 * (dom)))
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#define domain_val(dom,type) ((type) << (2 * (dom)))
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#ifdef CONFIG_CPU_SW_DOMAIN_PAN
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#define DACR_INIT \
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(domain_val(DOMAIN_USER, DOMAIN_NOACCESS) | \
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domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \
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domain_val(DOMAIN_IO, DOMAIN_CLIENT) | \
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domain_val(DOMAIN_VECTORS, DOMAIN_CLIENT))
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#else
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#define DACR_INIT \
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(domain_val(DOMAIN_USER, DOMAIN_CLIENT) | \
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domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \
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domain_val(DOMAIN_IO, DOMAIN_CLIENT) | \
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domain_val(DOMAIN_VECTORS, DOMAIN_CLIENT))
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#endif
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#define __DACR_DEFAULT \
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domain_val(DOMAIN_KERNEL, DOMAIN_CLIENT) | \
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domain_val(DOMAIN_IO, DOMAIN_CLIENT) | \
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domain_val(DOMAIN_VECTORS, DOMAIN_CLIENT)
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#define DACR_UACCESS_DISABLE \
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(__DACR_DEFAULT | domain_val(DOMAIN_USER, DOMAIN_NOACCESS))
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#define DACR_UACCESS_ENABLE \
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(__DACR_DEFAULT | domain_val(DOMAIN_USER, DOMAIN_CLIENT))
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#ifndef __ASSEMBLY__
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#ifdef CONFIG_CPU_CP15_MMU
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static __always_inline unsigned int get_domain(void)
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{
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unsigned int domain;
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asm(
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"mrc p15, 0, %0, c3, c0 @ get domain"
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: "=r" (domain)
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: "m" (current_thread_info()->cpu_domain));
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return domain;
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}
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static __always_inline void set_domain(unsigned int val)
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{
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asm volatile(
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"mcr p15, 0, %0, c3, c0 @ set domain"
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: : "r" (val) : "memory");
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isb();
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}
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#else
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static __always_inline unsigned int get_domain(void)
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{
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return 0;
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}
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static __always_inline void set_domain(unsigned int val)
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{
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}
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#endif
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/*
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* Generate the T (user) versions of the LDR/STR and related
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* instructions (inline assembly)
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*/
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#ifdef CONFIG_CPU_USE_DOMAINS
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#define TUSER(instr) TUSERCOND(instr, )
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#define TUSERCOND(instr, cond) #instr "t" #cond
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#else
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#define TUSER(instr) TUSERCOND(instr, )
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#define TUSERCOND(instr, cond) #instr #cond
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#endif
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#else /* __ASSEMBLY__ */
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/*
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* Generate the T (user) versions of the LDR/STR and related
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* instructions
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*/
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#ifdef CONFIG_CPU_USE_DOMAINS
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#define TUSER(instr) instr ## t
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#else
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#define TUSER(instr) instr
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* !__ASM_PROC_DOMAIN_H */
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