1d84afaf02
The fully ordered versions of xchg[8|16]() using LR/SC lack the
necessary memory barriers to guarantee the order.
Fix this by matching what is already implemented in the fully ordered
versions of cmpxchg() using LR/SC.
Suggested-by: Andrea Parri <parri.andrea@gmail.com>
Reported-by: Andrea Parri <parri.andrea@gmail.com>
Closes: https://lore.kernel.org/linux-riscv/ZlYbupL5XgzgA0MX@andrea/T/#u
Fixes: a8ed2b7a2c ("riscv/cmpxchg: Implement xchg for variables of size 1 and 2")
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Reviewed-by: Andrea Parri <parri.andrea@gmail.com>
Link: https://lore.kernel.org/r/20240530145546.394248-1-alexghiti@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
226 lines
6.1 KiB
C
226 lines
6.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2014 Regents of the University of California
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*/
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#ifndef _ASM_RISCV_CMPXCHG_H
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#define _ASM_RISCV_CMPXCHG_H
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#include <linux/bug.h>
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#include <asm/fence.h>
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#define __arch_xchg_masked(sc_sfx, prepend, append, r, p, n) \
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({ \
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u32 *__ptr32b = (u32 *)((ulong)(p) & ~0x3); \
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ulong __s = ((ulong)(p) & (0x4 - sizeof(*p))) * BITS_PER_BYTE; \
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ulong __mask = GENMASK(((sizeof(*p)) * BITS_PER_BYTE) - 1, 0) \
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<< __s; \
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ulong __newx = (ulong)(n) << __s; \
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ulong __retx; \
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ulong __rc; \
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\
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__asm__ __volatile__ ( \
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prepend \
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"0: lr.w %0, %2\n" \
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" and %1, %0, %z4\n" \
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" or %1, %1, %z3\n" \
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" sc.w" sc_sfx " %1, %1, %2\n" \
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" bnez %1, 0b\n" \
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append \
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: "=&r" (__retx), "=&r" (__rc), "+A" (*(__ptr32b)) \
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: "rJ" (__newx), "rJ" (~__mask) \
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: "memory"); \
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\
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r = (__typeof__(*(p)))((__retx & __mask) >> __s); \
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})
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#define __arch_xchg(sfx, prepend, append, r, p, n) \
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({ \
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__asm__ __volatile__ ( \
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prepend \
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" amoswap" sfx " %0, %2, %1\n" \
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append \
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: "=r" (r), "+A" (*(p)) \
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: "r" (n) \
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: "memory"); \
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})
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#define _arch_xchg(ptr, new, sc_sfx, swap_sfx, prepend, \
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sc_append, swap_append) \
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({ \
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__typeof__(ptr) __ptr = (ptr); \
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__typeof__(*(__ptr)) __new = (new); \
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__typeof__(*(__ptr)) __ret; \
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\
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switch (sizeof(*__ptr)) { \
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case 1: \
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case 2: \
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__arch_xchg_masked(sc_sfx, prepend, sc_append, \
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__ret, __ptr, __new); \
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break; \
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case 4: \
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__arch_xchg(".w" swap_sfx, prepend, swap_append, \
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__ret, __ptr, __new); \
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break; \
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case 8: \
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__arch_xchg(".d" swap_sfx, prepend, swap_append, \
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__ret, __ptr, __new); \
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break; \
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default: \
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BUILD_BUG(); \
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} \
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(__typeof__(*(__ptr)))__ret; \
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})
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#define arch_xchg_relaxed(ptr, x) \
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_arch_xchg(ptr, x, "", "", "", "", "")
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#define arch_xchg_acquire(ptr, x) \
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_arch_xchg(ptr, x, "", "", "", \
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RISCV_ACQUIRE_BARRIER, RISCV_ACQUIRE_BARRIER)
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#define arch_xchg_release(ptr, x) \
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_arch_xchg(ptr, x, "", "", RISCV_RELEASE_BARRIER, "", "")
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#define arch_xchg(ptr, x) \
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_arch_xchg(ptr, x, ".rl", ".aqrl", "", RISCV_FULL_BARRIER, "")
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#define xchg32(ptr, x) \
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({ \
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BUILD_BUG_ON(sizeof(*(ptr)) != 4); \
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arch_xchg((ptr), (x)); \
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})
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#define xchg64(ptr, x) \
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({ \
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BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
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arch_xchg((ptr), (x)); \
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})
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/*
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* Atomic compare and exchange. Compare OLD with MEM, if identical,
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* store NEW in MEM. Return the initial value in MEM. Success is
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* indicated by comparing RETURN with OLD.
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*/
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#define __arch_cmpxchg_masked(sc_sfx, prepend, append, r, p, o, n) \
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({ \
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u32 *__ptr32b = (u32 *)((ulong)(p) & ~0x3); \
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ulong __s = ((ulong)(p) & (0x4 - sizeof(*p))) * BITS_PER_BYTE; \
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ulong __mask = GENMASK(((sizeof(*p)) * BITS_PER_BYTE) - 1, 0) \
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<< __s; \
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ulong __newx = (ulong)(n) << __s; \
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ulong __oldx = (ulong)(o) << __s; \
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ulong __retx; \
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ulong __rc; \
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\
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__asm__ __volatile__ ( \
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prepend \
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"0: lr.w %0, %2\n" \
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" and %1, %0, %z5\n" \
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" bne %1, %z3, 1f\n" \
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" and %1, %0, %z6\n" \
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" or %1, %1, %z4\n" \
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" sc.w" sc_sfx " %1, %1, %2\n" \
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" bnez %1, 0b\n" \
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append \
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"1:\n" \
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: "=&r" (__retx), "=&r" (__rc), "+A" (*(__ptr32b)) \
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: "rJ" ((long)__oldx), "rJ" (__newx), \
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"rJ" (__mask), "rJ" (~__mask) \
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: "memory"); \
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\
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r = (__typeof__(*(p)))((__retx & __mask) >> __s); \
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})
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#define __arch_cmpxchg(lr_sfx, sc_sfx, prepend, append, r, p, co, o, n) \
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({ \
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register unsigned int __rc; \
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\
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__asm__ __volatile__ ( \
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prepend \
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"0: lr" lr_sfx " %0, %2\n" \
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" bne %0, %z3, 1f\n" \
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" sc" sc_sfx " %1, %z4, %2\n" \
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" bnez %1, 0b\n" \
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append \
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"1:\n" \
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: "=&r" (r), "=&r" (__rc), "+A" (*(p)) \
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: "rJ" (co o), "rJ" (n) \
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: "memory"); \
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})
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#define _arch_cmpxchg(ptr, old, new, sc_sfx, prepend, append) \
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({ \
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__typeof__(ptr) __ptr = (ptr); \
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__typeof__(*(__ptr)) __old = (old); \
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__typeof__(*(__ptr)) __new = (new); \
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__typeof__(*(__ptr)) __ret; \
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\
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switch (sizeof(*__ptr)) { \
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case 1: \
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case 2: \
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__arch_cmpxchg_masked(sc_sfx, prepend, append, \
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__ret, __ptr, __old, __new); \
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break; \
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case 4: \
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__arch_cmpxchg(".w", ".w" sc_sfx, prepend, append, \
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__ret, __ptr, (long), __old, __new); \
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break; \
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case 8: \
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__arch_cmpxchg(".d", ".d" sc_sfx, prepend, append, \
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__ret, __ptr, /**/, __old, __new); \
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break; \
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default: \
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BUILD_BUG(); \
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} \
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(__typeof__(*(__ptr)))__ret; \
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})
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#define arch_cmpxchg_relaxed(ptr, o, n) \
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_arch_cmpxchg((ptr), (o), (n), "", "", "")
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#define arch_cmpxchg_acquire(ptr, o, n) \
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_arch_cmpxchg((ptr), (o), (n), "", "", RISCV_ACQUIRE_BARRIER)
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#define arch_cmpxchg_release(ptr, o, n) \
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_arch_cmpxchg((ptr), (o), (n), "", RISCV_RELEASE_BARRIER, "")
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#define arch_cmpxchg(ptr, o, n) \
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_arch_cmpxchg((ptr), (o), (n), ".rl", "", " fence rw, rw\n")
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#define arch_cmpxchg_local(ptr, o, n) \
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arch_cmpxchg_relaxed((ptr), (o), (n))
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#define arch_cmpxchg64(ptr, o, n) \
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({ \
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BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
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arch_cmpxchg((ptr), (o), (n)); \
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})
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#define arch_cmpxchg64_local(ptr, o, n) \
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({ \
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BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
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arch_cmpxchg_relaxed((ptr), (o), (n)); \
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})
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#define arch_cmpxchg64_relaxed(ptr, o, n) \
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({ \
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BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
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arch_cmpxchg_relaxed((ptr), (o), (n)); \
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})
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#define arch_cmpxchg64_acquire(ptr, o, n) \
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({ \
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BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
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arch_cmpxchg_acquire((ptr), (o), (n)); \
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})
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#define arch_cmpxchg64_release(ptr, o, n) \
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({ \
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BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
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arch_cmpxchg_release((ptr), (o), (n)); \
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})
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#endif /* _ASM_RISCV_CMPXCHG_H */
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