c150b809f7
* Support for various vector-accelerated crypto routines.
* Hibernation is now enabled for portable kernel builds.
* mmap_rnd_bits_max is larger on systems with larger VAs.
* Support for fast GUP.
* Support for membarrier-based instruction cache synchronization.
* Support for the Andes hart-level interrupt controller and PMU.
* Some cleanups around unaligned access speed probing and Kconfig
settings.
* Support for ACPI LPI and CPPC.
* Various cleanus related to barriers.
* A handful of fixes.
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Merge tag 'riscv-for-linus-6.9-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
Pull RISC-V updates from Palmer Dabbelt:
- Support for various vector-accelerated crypto routines
- Hibernation is now enabled for portable kernel builds
- mmap_rnd_bits_max is larger on systems with larger VAs
- Support for fast GUP
- Support for membarrier-based instruction cache synchronization
- Support for the Andes hart-level interrupt controller and PMU
- Some cleanups around unaligned access speed probing and Kconfig
settings
- Support for ACPI LPI and CPPC
- Various cleanus related to barriers
- A handful of fixes
* tag 'riscv-for-linus-6.9-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (66 commits)
riscv: Fix syscall wrapper for >word-size arguments
crypto: riscv - add vector crypto accelerated AES-CBC-CTS
crypto: riscv - parallelize AES-CBC decryption
riscv: Only flush the mm icache when setting an exec pte
riscv: Use kcalloc() instead of kzalloc()
riscv/barrier: Add missing space after ','
riscv/barrier: Consolidate fence definitions
riscv/barrier: Define RISCV_FULL_BARRIER
riscv/barrier: Define __{mb,rmb,wmb}
RISC-V: defconfig: Enable CONFIG_ACPI_CPPC_CPUFREQ
cpufreq: Move CPPC configs to common Kconfig and add RISC-V
ACPI: RISC-V: Add CPPC driver
ACPI: Enable ACPI_PROCESSOR for RISC-V
ACPI: RISC-V: Add LPI driver
cpuidle: RISC-V: Move few functions to arch/riscv
riscv: Introduce set_compat_task() in asm/compat.h
riscv: Introduce is_compat_thread() into compat.h
riscv: add compile-time test into is_compat_task()
riscv: Replace direct thread flag check with is_compat_task()
riscv: Improve arch_get_mmap_end() macro
...
147 lines
3.4 KiB
C
147 lines
3.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright 2022-2024 Rivos, Inc
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*/
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#ifndef _ASM_CPUFEATURE_H
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#define _ASM_CPUFEATURE_H
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#include <linux/bitmap.h>
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#include <linux/jump_label.h>
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#include <asm/hwcap.h>
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#include <asm/alternative-macros.h>
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#include <asm/errno.h>
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/*
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* These are probed via a device_initcall(), via either the SBI or directly
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* from the corresponding CSRs.
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*/
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struct riscv_cpuinfo {
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unsigned long mvendorid;
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unsigned long marchid;
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unsigned long mimpid;
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};
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struct riscv_isainfo {
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DECLARE_BITMAP(isa, RISCV_ISA_EXT_MAX);
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};
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DECLARE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo);
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/* Per-cpu ISA extensions. */
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extern struct riscv_isainfo hart_isa[NR_CPUS];
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void riscv_user_isa_enable(void);
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#if defined(CONFIG_RISCV_MISALIGNED)
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bool check_unaligned_access_emulated_all_cpus(void);
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void unaligned_emulation_finish(void);
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bool unaligned_ctl_available(void);
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DECLARE_PER_CPU(long, misaligned_access_speed);
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#else
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static inline bool unaligned_ctl_available(void)
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{
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return false;
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}
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#endif
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#if defined(CONFIG_RISCV_PROBE_UNALIGNED_ACCESS)
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DECLARE_STATIC_KEY_FALSE(fast_unaligned_access_speed_key);
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static __always_inline bool has_fast_unaligned_accesses(void)
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{
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return static_branch_likely(&fast_unaligned_access_speed_key);
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}
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#else
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static __always_inline bool has_fast_unaligned_accesses(void)
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{
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if (IS_ENABLED(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS))
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return true;
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else
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return false;
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}
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#endif
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unsigned long riscv_get_elf_hwcap(void);
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struct riscv_isa_ext_data {
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const unsigned int id;
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const char *name;
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const char *property;
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const unsigned int *subset_ext_ids;
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const unsigned int subset_ext_size;
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};
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extern const struct riscv_isa_ext_data riscv_isa_ext[];
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extern const size_t riscv_isa_ext_count;
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extern bool riscv_isa_fallback;
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unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap);
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bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, unsigned int bit);
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#define riscv_isa_extension_available(isa_bitmap, ext) \
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__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_##ext)
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static __always_inline bool
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riscv_has_extension_likely(const unsigned long ext)
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{
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compiletime_assert(ext < RISCV_ISA_EXT_MAX,
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"ext must be < RISCV_ISA_EXT_MAX");
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if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) {
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asm goto(
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ALTERNATIVE("j %l[l_no]", "nop", 0, %[ext], 1)
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:
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: [ext] "i" (ext)
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:
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: l_no);
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} else {
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if (!__riscv_isa_extension_available(NULL, ext))
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goto l_no;
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}
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return true;
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l_no:
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return false;
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}
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static __always_inline bool
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riscv_has_extension_unlikely(const unsigned long ext)
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{
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compiletime_assert(ext < RISCV_ISA_EXT_MAX,
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"ext must be < RISCV_ISA_EXT_MAX");
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if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) {
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asm goto(
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ALTERNATIVE("nop", "j %l[l_yes]", 0, %[ext], 1)
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:
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: [ext] "i" (ext)
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:
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: l_yes);
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} else {
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if (__riscv_isa_extension_available(NULL, ext))
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goto l_yes;
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}
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return false;
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l_yes:
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return true;
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}
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static __always_inline bool riscv_cpu_has_extension_likely(int cpu, const unsigned long ext)
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{
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if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE) && riscv_has_extension_likely(ext))
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return true;
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return __riscv_isa_extension_available(hart_isa[cpu].isa, ext);
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}
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static __always_inline bool riscv_cpu_has_extension_unlikely(int cpu, const unsigned long ext)
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{
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if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE) && riscv_has_extension_unlikely(ext))
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return true;
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return __riscv_isa_extension_available(hart_isa[cpu].isa, ext);
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}
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#endif
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