edf9556472
As very well explained in commit 20a004e7b0 ("arm64: mm: Use
READ_ONCE/WRITE_ONCE when accessing page tables"), an architecture whose
page table walker can modify the PTE in parallel must use
READ_ONCE()/WRITE_ONCE() macro to avoid any compiler transformation.
So apply that to riscv which is such architecture.
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Acked-by: Anup Patel <anup@brainfault.org>
Link: https://lore.kernel.org/r/20231213203001.179237-5-alexghiti@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
30 lines
629 B
C
30 lines
629 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_RISCV_KFENCE_H
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#define _ASM_RISCV_KFENCE_H
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#include <linux/kfence.h>
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#include <linux/pfn.h>
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#include <asm-generic/pgalloc.h>
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#include <asm/pgtable.h>
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static inline bool arch_kfence_init_pool(void)
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{
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return true;
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}
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static inline bool kfence_protect_page(unsigned long addr, bool protect)
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{
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pte_t *pte = virt_to_kpte(addr);
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if (protect)
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set_pte(pte, __pte(pte_val(ptep_get(pte)) & ~_PAGE_PRESENT));
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else
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set_pte(pte, __pte(pte_val(ptep_get(pte)) | _PAGE_PRESENT));
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flush_tlb_kernel_range(addr, addr + PAGE_SIZE);
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return true;
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}
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#endif /* _ASM_RISCV_KFENCE_H */
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