1b03d82ba1
All MSI vectors are multiplexed into a single notification vector when
posted MSI is enabled. It is the responsibility of the notification vector
handler to demultiplex MSI vectors. In the handler the MSI vector handlers
are dispatched without IDT delivery for each pending MSI interrupt.
For example, the interrupt flow will change as follows:
(3 MSIs of different vectors arrive in a a high frequency burst)
BEFORE:
interrupt(MSI)
irq_enter()
handler() /* EOI */
irq_exit()
process_softirq()
interrupt(MSI)
irq_enter()
handler() /* EOI */
irq_exit()
process_softirq()
interrupt(MSI)
irq_enter()
handler() /* EOI */
irq_exit()
process_softirq()
AFTER:
interrupt /* Posted MSI notification vector */
irq_enter()
atomic_xchg(PIR)
handler()
handler()
handler()
pi_clear_on()
apic_eoi()
irq_exit()
process_softirq()
Except for the leading MSI, CPU notifications are skipped/coalesced.
For MSIs which arrive at a low frequency, the demultiplexing loop does not
wait for more interrupts to coalesce. Therefore, there's no additional
latency other than the processing time.
Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/r/20240423174114.526704-9-jacob.jun.pan@linux.intel.com
90 lines
2.4 KiB
C
90 lines
2.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_X86_HARDIRQ_H
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#define _ASM_X86_HARDIRQ_H
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#include <linux/threads.h>
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#include <asm/current.h>
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typedef struct {
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#if IS_ENABLED(CONFIG_KVM_INTEL)
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u8 kvm_cpu_l1tf_flush_l1d;
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#endif
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unsigned int __nmi_count; /* arch dependent */
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#ifdef CONFIG_X86_LOCAL_APIC
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unsigned int apic_timer_irqs; /* arch dependent */
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unsigned int irq_spurious_count;
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unsigned int icr_read_retry_count;
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#endif
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#if IS_ENABLED(CONFIG_KVM)
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unsigned int kvm_posted_intr_ipis;
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unsigned int kvm_posted_intr_wakeup_ipis;
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unsigned int kvm_posted_intr_nested_ipis;
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#endif
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unsigned int x86_platform_ipis; /* arch dependent */
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unsigned int apic_perf_irqs;
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unsigned int apic_irq_work_irqs;
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#ifdef CONFIG_SMP
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unsigned int irq_resched_count;
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unsigned int irq_call_count;
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#endif
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unsigned int irq_tlb_count;
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#ifdef CONFIG_X86_THERMAL_VECTOR
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unsigned int irq_thermal_count;
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#endif
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#ifdef CONFIG_X86_MCE_THRESHOLD
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unsigned int irq_threshold_count;
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#endif
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#ifdef CONFIG_X86_MCE_AMD
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unsigned int irq_deferred_error_count;
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#endif
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#ifdef CONFIG_X86_HV_CALLBACK_VECTOR
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unsigned int irq_hv_callback_count;
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#endif
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#if IS_ENABLED(CONFIG_HYPERV)
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unsigned int irq_hv_reenlightenment_count;
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unsigned int hyperv_stimer0_count;
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#endif
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#ifdef CONFIG_X86_POSTED_MSI
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unsigned int posted_msi_notification_count;
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#endif
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} ____cacheline_aligned irq_cpustat_t;
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DECLARE_PER_CPU_SHARED_ALIGNED(irq_cpustat_t, irq_stat);
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#ifdef CONFIG_X86_POSTED_MSI
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DECLARE_PER_CPU_ALIGNED(struct pi_desc, posted_msi_pi_desc);
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#endif
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#define __ARCH_IRQ_STAT
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#define inc_irq_stat(member) this_cpu_inc(irq_stat.member)
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extern void ack_bad_irq(unsigned int irq);
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extern u64 arch_irq_stat_cpu(unsigned int cpu);
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#define arch_irq_stat_cpu arch_irq_stat_cpu
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extern u64 arch_irq_stat(void);
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#define arch_irq_stat arch_irq_stat
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#define local_softirq_pending_ref pcpu_hot.softirq_pending
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#if IS_ENABLED(CONFIG_KVM_INTEL)
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static inline void kvm_set_cpu_l1tf_flush_l1d(void)
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{
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__this_cpu_write(irq_stat.kvm_cpu_l1tf_flush_l1d, 1);
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}
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static __always_inline void kvm_clear_cpu_l1tf_flush_l1d(void)
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{
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__this_cpu_write(irq_stat.kvm_cpu_l1tf_flush_l1d, 0);
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}
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static __always_inline bool kvm_get_cpu_l1tf_flush_l1d(void)
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{
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return __this_cpu_read(irq_stat.kvm_cpu_l1tf_flush_l1d);
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}
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#else /* !IS_ENABLED(CONFIG_KVM_INTEL) */
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static inline void kvm_set_cpu_l1tf_flush_l1d(void) { }
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#endif /* IS_ENABLED(CONFIG_KVM_INTEL) */
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#endif /* _ASM_X86_HARDIRQ_H */
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