a815362752
On MTL the GOP (for whatever reason) likes to bind its framebuffer
high up in the ggtt address space. This can conflict with whatever
ggtt_reserve_guc_top() is trying to do, and the result is that
ggtt_reserve_guc_top() fails and then we proceed to explode when
trying to tear down the driver. Thus far I haven't analyzed what
causes the actual fireworks, but it's not super important as even
if it didn't explode we'd still fail the driver load and the user
would be left with an unusable GPU.
To remedy this (without having to figure out exactly what
ggtt_reserve_guc_top() is trying to achieve) we can attempt to
relocate the BIOS framebuffer to a lower ggtt address. We can do
this at this early point in driver init because nothing else is
supposed to be clobbering the ggtt yet. So we simply change where
in the ggtt we pin the vma, the original PTEs will be left as is,
and the new PTEs will get written with the same dma addresses.
The plane will keep on scanning out from the original PTEs until
we are done with the whole process, and at that point we rewrite
the plane's surface address register to point at the new ggtt
address.
Since we don't need a specific ggtt address for the plane
(apart from needing it to land in the mappable region for
normal stolen objects) we'll just try to pin it without a fixed
offset first. It should end up at the lowest available address
(which really should be 0 at this point in the driver init).
If that fails we'll fall back to just pinning it exactly to the
origianal address.
To make sure we don't accidentlally pin it partially over the
original ggtt range (as that would corrupt the original PTEs)
we reserve the original range temporarily during this process.
v2: Try to pin explicitly to ggtt offset 0 as otherwise DG2 puts it
even higher (atm we have no PIN_LOW flag to force it low)
v3: "fix" xe
Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
Tested-by: Paz Zcharya <pazz@chromium.org>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240202224340.30647-16-ville.syrjala@linux.intel.com
Acked-by: Lucas De Marchi <lucas.demarchi@intel.com>
38 lines
1 KiB
C
38 lines
1 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2020 Intel Corporation
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*/
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#ifndef _SKL_UNIVERSAL_PLANE_H_
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#define _SKL_UNIVERSAL_PLANE_H_
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#include <linux/types.h>
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struct drm_i915_private;
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struct intel_crtc;
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struct intel_initial_plane_config;
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struct intel_plane_state;
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enum pipe;
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enum plane_id;
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struct intel_plane *
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skl_universal_plane_create(struct drm_i915_private *dev_priv,
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enum pipe pipe, enum plane_id plane_id);
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void skl_get_initial_plane_config(struct intel_crtc *crtc,
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struct intel_initial_plane_config *plane_config);
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bool skl_fixup_initial_plane_config(struct intel_crtc *crtc,
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const struct intel_initial_plane_config *plane_config);
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int skl_format_to_fourcc(int format, bool rgb_order, bool alpha);
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int skl_calc_main_surface_offset(const struct intel_plane_state *plane_state,
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int *x, int *y, u32 *offset);
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bool icl_is_nv12_y_plane(struct drm_i915_private *dev_priv,
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enum plane_id plane_id);
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u8 icl_hdr_plane_mask(void);
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bool icl_is_hdr_plane(struct drm_i915_private *dev_priv, enum plane_id plane_id);
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#endif
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