682aa4373f
With GuC mode of submission, GuC is in control of defining the context id field that is part of the OA reports. To filter reports, UMD and KMD must know what sw context id was chosen by GuC. There is not interface between KMD and GuC to determine this, so read the upper-dword of EXECLIST_STATUS to filter/squash OA reports for the specific context. v2: Explain guc id stealing w.r.t OA use case Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com> Signed-off-by: John Harrison <John.C.Harrison@Intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20221026222102.5526-2-umesh.nerlige.ramappa@intel.com
145 lines
4 KiB
C
145 lines
4 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2014 Intel Corporation
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*/
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#ifndef __INTEL_LRC_H__
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#define __INTEL_LRC_H__
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#include "i915_priolist_types.h"
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#include <linux/bitfield.h>
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#include <linux/types.h>
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#include "intel_context.h"
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struct drm_i915_gem_object;
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struct i915_gem_ww_ctx;
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struct intel_engine_cs;
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struct intel_ring;
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struct kref;
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/* At the start of the context image is its per-process HWS page */
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#define LRC_PPHWSP_PN (0)
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#define LRC_PPHWSP_SZ (1)
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/* After the PPHWSP we have the logical state for the context */
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#define LRC_STATE_PN (LRC_PPHWSP_PN + LRC_PPHWSP_SZ)
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#define LRC_STATE_OFFSET (LRC_STATE_PN * PAGE_SIZE)
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/* Space within PPHWSP reserved to be used as scratch */
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#define LRC_PPHWSP_SCRATCH 0x34
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#define LRC_PPHWSP_SCRATCH_ADDR (LRC_PPHWSP_SCRATCH * sizeof(u32))
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void lrc_init_wa_ctx(struct intel_engine_cs *engine);
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void lrc_fini_wa_ctx(struct intel_engine_cs *engine);
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int lrc_alloc(struct intel_context *ce,
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struct intel_engine_cs *engine);
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void lrc_reset(struct intel_context *ce);
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void lrc_fini(struct intel_context *ce);
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void lrc_destroy(struct kref *kref);
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int
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lrc_pre_pin(struct intel_context *ce,
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struct intel_engine_cs *engine,
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struct i915_gem_ww_ctx *ww,
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void **vaddr);
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int
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lrc_pin(struct intel_context *ce,
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struct intel_engine_cs *engine,
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void *vaddr);
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void lrc_unpin(struct intel_context *ce);
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void lrc_post_unpin(struct intel_context *ce);
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void lrc_init_state(struct intel_context *ce,
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struct intel_engine_cs *engine,
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void *state);
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void lrc_init_regs(const struct intel_context *ce,
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const struct intel_engine_cs *engine,
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bool clear);
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void lrc_reset_regs(const struct intel_context *ce,
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const struct intel_engine_cs *engine);
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u32 lrc_update_regs(const struct intel_context *ce,
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const struct intel_engine_cs *engine,
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u32 head);
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void lrc_update_offsets(struct intel_context *ce,
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struct intel_engine_cs *engine);
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void lrc_check_regs(const struct intel_context *ce,
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const struct intel_engine_cs *engine,
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const char *when);
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void lrc_update_runtime(struct intel_context *ce);
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enum {
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INTEL_ADVANCED_CONTEXT = 0,
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INTEL_LEGACY_32B_CONTEXT,
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INTEL_ADVANCED_AD_CONTEXT,
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INTEL_LEGACY_64B_CONTEXT
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};
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enum {
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FAULT_AND_HANG = 0,
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FAULT_AND_HALT, /* Debug only */
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FAULT_AND_STREAM,
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FAULT_AND_CONTINUE /* Unsupported */
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};
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#define CTX_GTT_ADDRESS_MASK GENMASK(31, 12)
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#define GEN8_CTX_VALID (1 << 0)
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#define GEN8_CTX_FORCE_PD_RESTORE (1 << 1)
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#define GEN8_CTX_FORCE_RESTORE (1 << 2)
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#define GEN8_CTX_L3LLC_COHERENT (1 << 5)
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#define GEN8_CTX_PRIVILEGE (1 << 8)
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#define GEN8_CTX_ADDRESSING_MODE_SHIFT 3
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#define GEN12_CTX_PRIORITY_MASK GENMASK(10, 9)
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#define GEN12_CTX_PRIORITY_HIGH FIELD_PREP(GEN12_CTX_PRIORITY_MASK, 2)
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#define GEN12_CTX_PRIORITY_NORMAL FIELD_PREP(GEN12_CTX_PRIORITY_MASK, 1)
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#define GEN12_CTX_PRIORITY_LOW FIELD_PREP(GEN12_CTX_PRIORITY_MASK, 0)
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#define GEN8_CTX_ID_SHIFT 32
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#define GEN8_CTX_ID_WIDTH 21
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#define GEN11_SW_CTX_ID_SHIFT 37
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#define GEN11_SW_CTX_ID_WIDTH 11
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#define GEN11_ENGINE_CLASS_SHIFT 61
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#define GEN11_ENGINE_CLASS_WIDTH 3
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#define GEN11_ENGINE_INSTANCE_SHIFT 48
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#define GEN11_ENGINE_INSTANCE_WIDTH 6
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#define XEHP_SW_CTX_ID_SHIFT 39
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#define XEHP_SW_CTX_ID_WIDTH 16
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#define XEHP_SW_COUNTER_SHIFT 58
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#define XEHP_SW_COUNTER_WIDTH 6
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#define GEN12_GUC_SW_CTX_ID_SHIFT 39
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#define GEN12_GUC_SW_CTX_ID_WIDTH 16
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static inline void lrc_runtime_start(struct intel_context *ce)
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{
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struct intel_context_stats *stats = &ce->stats;
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if (intel_context_is_barrier(ce))
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return;
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if (stats->active)
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return;
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WRITE_ONCE(stats->active, intel_context_clock());
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}
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static inline void lrc_runtime_stop(struct intel_context *ce)
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{
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struct intel_context_stats *stats = &ce->stats;
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if (!stats->active)
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return;
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lrc_update_runtime(ce);
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WRITE_ONCE(stats->active, 0);
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}
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#define DG2_PREDICATE_RESULT_WA (PAGE_SIZE - sizeof(u64))
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#define DG2_PREDICATE_RESULT_BB (2048)
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u32 lrc_indirect_bb(const struct intel_context *ce);
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#endif /* __INTEL_LRC_H__ */
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