8f76c0f4c3
Currently big amount of the functions returning standard error codes are of type s32. Convert them to regular ints as typdefs here are not necessary to return standard error codes. Fix incorrect args alignment in touched functions. Suggested-by: Jacob Keller <jacob.e.keller@intel.com> Reviewed-by: Jacob Keller <jacob.e.keller@intel.com> Reviewed-by: Simon Horman <horms@kernel.org> Signed-off-by: Jedrzej Jagielski <jedrzej.jagielski@intel.com> Tested-by: Pucha Himasekhar Reddy <himasekharx.reddy.pucha@intel.com> (A Contingent worker at Intel) Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
64 lines
2.5 KiB
C
64 lines
2.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright(c) 1999 - 2018 Intel Corporation. */
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#ifndef _DCB_82598_CONFIG_H_
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#define _DCB_82598_CONFIG_H_
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/* DCB register definitions */
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#define IXGBE_DPMCS_MTSOS_SHIFT 16
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#define IXGBE_DPMCS_TDPAC 0x00000001 /* 0 Round Robin, 1 DFP - Deficit Fixed Priority */
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#define IXGBE_DPMCS_TRM 0x00000010 /* Transmit Recycle Mode */
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#define IXGBE_DPMCS_ARBDIS 0x00000040 /* DCB arbiter disable */
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#define IXGBE_DPMCS_TSOEF 0x00080000 /* TSO Expand Factor: 0=x4, 1=x2 */
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#define IXGBE_RUPPBMR_MQA 0x80000000 /* Enable UP to queue mapping */
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#define IXGBE_RT2CR_MCL_SHIFT 12 /* Offset to Max Credit Limit setting */
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#define IXGBE_RT2CR_LSP 0x80000000 /* LSP enable bit */
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#define IXGBE_RDRXCTL_MPBEN 0x00000010 /* DMA config for multiple packet buffers enable */
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#define IXGBE_RDRXCTL_MCEN 0x00000040 /* DMA config for multiple cores (RSS) enable */
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#define IXGBE_TDTQ2TCCR_MCL_SHIFT 12
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#define IXGBE_TDTQ2TCCR_BWG_SHIFT 9
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#define IXGBE_TDTQ2TCCR_GSP 0x40000000
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#define IXGBE_TDTQ2TCCR_LSP 0x80000000
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#define IXGBE_TDPT2TCCR_MCL_SHIFT 12
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#define IXGBE_TDPT2TCCR_BWG_SHIFT 9
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#define IXGBE_TDPT2TCCR_GSP 0x40000000
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#define IXGBE_TDPT2TCCR_LSP 0x80000000
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#define IXGBE_PDPMCS_TPPAC 0x00000020 /* 0 Round Robin, 1 for DFP - Deficit Fixed Priority */
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#define IXGBE_PDPMCS_ARBDIS 0x00000040 /* Arbiter disable */
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#define IXGBE_PDPMCS_TRM 0x00000100 /* Transmit Recycle Mode enable */
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#define IXGBE_DTXCTL_ENDBUBD 0x00000004 /* Enable DBU buffer division */
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#define IXGBE_TXPBSIZE_40KB 0x0000A000 /* 40KB Packet Buffer */
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#define IXGBE_RXPBSIZE_48KB 0x0000C000 /* 48KB Packet Buffer */
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#define IXGBE_RXPBSIZE_64KB 0x00010000 /* 64KB Packet Buffer */
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#define IXGBE_RXPBSIZE_80KB 0x00014000 /* 80KB Packet Buffer */
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#define IXGBE_RDRXCTL_RDMTS_1_2 0x00000000
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/* DCB hardware-specific driver APIs */
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/* DCB PFC functions */
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int ixgbe_dcb_config_pfc_82598(struct ixgbe_hw *, u8 pfc_en);
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/* DCB hw initialization */
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int ixgbe_dcb_config_rx_arbiter_82598(struct ixgbe_hw *hw, u16 *refill,
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u16 *max, u8 *prio_type);
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int ixgbe_dcb_config_tx_desc_arbiter_82598(struct ixgbe_hw *hw, u16 *refill,
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u16 *max, u8 *bwg_id, u8 *prio_type);
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int ixgbe_dcb_config_tx_data_arbiter_82598(struct ixgbe_hw *hw, u16 *refill,
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u16 *max, u8 *bwg_id, u8 *prio_type);
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int ixgbe_dcb_hw_config_82598(struct ixgbe_hw *hw, u8 pfc_en, u16 *refill,
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u16 *max, u8 *bwg_id, u8 *prio_type);
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#endif /* _DCB_82598_CONFIG_H */
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