2e45d404d9
Deatch qca83xx PHY driver from at803x. The QCA83xx PHYs implement specific function and doesn't use generic at803x so it can be detached from the driver and moved to a dedicated one. Probe function and priv struct is reimplemented to allocate and use only the qca83xx specific data. Unused data from at803x PHY driver are dropped from at803x priv struct. This is to make slimmer PHY drivers instead of including lots of bloat that would never be used in specific SoC. A new Kconfig flag QCA83XX_PHY is introduced to compile the new introduced PHY driver. As the Kconfig name starts with Qualcomm the same order is kept. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://lore.kernel.org/r/20240129141600.2592-4-ansuelsmth@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
275 lines
7 KiB
C
275 lines
7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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#include <linux/phy.h>
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#include <linux/module.h>
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#include "qcom.h"
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#define AT803X_DEBUG_REG_3C 0x3C
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#define AT803X_DEBUG_REG_GREEN 0x3D
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#define AT803X_DEBUG_GATE_CLK_IN1000 BIT(6)
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#define MDIO_AZ_DEBUG 0x800D
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#define QCA8327_A_PHY_ID 0x004dd033
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#define QCA8327_B_PHY_ID 0x004dd034
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#define QCA8337_PHY_ID 0x004dd036
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#define QCA8K_PHY_ID_MASK 0xffffffff
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#define QCA8K_DEVFLAGS_REVISION_MASK GENMASK(2, 0)
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static struct at803x_hw_stat qca83xx_hw_stats[] = {
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{ "phy_idle_errors", 0xa, GENMASK(7, 0), PHY},
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{ "phy_receive_errors", 0x15, GENMASK(15, 0), PHY},
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{ "eee_wake_errors", 0x16, GENMASK(15, 0), MMD},
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};
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struct qca83xx_priv {
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u64 stats[ARRAY_SIZE(qca83xx_hw_stats)];
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};
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MODULE_DESCRIPTION("Qualcomm Atheros QCA83XX PHY driver");
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MODULE_AUTHOR("Matus Ujhelyi");
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MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>");
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MODULE_LICENSE("GPL");
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static int qca83xx_get_sset_count(struct phy_device *phydev)
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{
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return ARRAY_SIZE(qca83xx_hw_stats);
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}
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static void qca83xx_get_strings(struct phy_device *phydev, u8 *data)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(qca83xx_hw_stats); i++) {
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strscpy(data + i * ETH_GSTRING_LEN,
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qca83xx_hw_stats[i].string, ETH_GSTRING_LEN);
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}
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}
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static u64 qca83xx_get_stat(struct phy_device *phydev, int i)
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{
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struct at803x_hw_stat stat = qca83xx_hw_stats[i];
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struct qca83xx_priv *priv = phydev->priv;
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int val;
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u64 ret;
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if (stat.access_type == MMD)
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val = phy_read_mmd(phydev, MDIO_MMD_PCS, stat.reg);
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else
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val = phy_read(phydev, stat.reg);
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if (val < 0) {
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ret = U64_MAX;
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} else {
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val = val & stat.mask;
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priv->stats[i] += val;
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ret = priv->stats[i];
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}
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return ret;
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}
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static void qca83xx_get_stats(struct phy_device *phydev,
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struct ethtool_stats *stats, u64 *data)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(qca83xx_hw_stats); i++)
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data[i] = qca83xx_get_stat(phydev, i);
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}
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static int qca83xx_probe(struct phy_device *phydev)
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{
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struct device *dev = &phydev->mdio.dev;
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struct qca83xx_priv *priv;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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phydev->priv = priv;
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return 0;
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}
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static int qca83xx_config_init(struct phy_device *phydev)
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{
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u8 switch_revision;
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switch_revision = phydev->dev_flags & QCA8K_DEVFLAGS_REVISION_MASK;
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switch (switch_revision) {
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case 1:
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/* For 100M waveform */
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at803x_debug_reg_write(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0x02ea);
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/* Turn on Gigabit clock */
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at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, 0x68a0);
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break;
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case 2:
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phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0x0);
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fallthrough;
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case 4:
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phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_AZ_DEBUG, 0x803f);
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at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, 0x6860);
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at803x_debug_reg_write(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 0x2c46);
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at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_3C, 0x6000);
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break;
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}
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/* Following original QCA sourcecode set port to prefer master */
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phy_set_bits(phydev, MII_CTRL1000, CTL1000_PREFER_MASTER);
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return 0;
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}
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static int qca8327_config_init(struct phy_device *phydev)
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{
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/* QCA8327 require DAC amplitude adjustment for 100m set to +6%.
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* Disable on init and enable only with 100m speed following
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* qca original source code.
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*/
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at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
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QCA8327_DEBUG_MANU_CTRL_EN, 0);
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return qca83xx_config_init(phydev);
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}
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static void qca83xx_link_change_notify(struct phy_device *phydev)
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{
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/* Set DAC Amplitude adjustment to +6% for 100m on link running */
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if (phydev->state == PHY_RUNNING) {
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if (phydev->speed == SPEED_100)
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at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
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QCA8327_DEBUG_MANU_CTRL_EN,
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QCA8327_DEBUG_MANU_CTRL_EN);
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} else {
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/* Reset DAC Amplitude adjustment */
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at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
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QCA8327_DEBUG_MANU_CTRL_EN, 0);
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}
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}
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static int qca83xx_resume(struct phy_device *phydev)
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{
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int ret, val;
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/* Skip reset if not suspended */
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if (!phydev->suspended)
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return 0;
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/* Reinit the port, reset values set by suspend */
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qca83xx_config_init(phydev);
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/* Reset the port on port resume */
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phy_set_bits(phydev, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
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/* On resume from suspend the switch execute a reset and
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* restart auto-negotiation. Wait for reset to complete.
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*/
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ret = phy_read_poll_timeout(phydev, MII_BMCR, val, !(val & BMCR_RESET),
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50000, 600000, true);
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if (ret)
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return ret;
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usleep_range(1000, 2000);
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return 0;
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}
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static int qca83xx_suspend(struct phy_device *phydev)
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{
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at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_GREEN,
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AT803X_DEBUG_GATE_CLK_IN1000, 0);
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at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_HIB_CTRL,
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AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE |
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AT803X_DEBUG_HIB_CTRL_SEL_RST_80U, 0);
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return 0;
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}
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static int qca8337_suspend(struct phy_device *phydev)
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{
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/* Only QCA8337 support actual suspend. */
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genphy_suspend(phydev);
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return qca83xx_suspend(phydev);
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}
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static int qca8327_suspend(struct phy_device *phydev)
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{
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u16 mask = 0;
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/* QCA8327 cause port unreliability when phy suspend
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* is set.
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*/
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mask |= ~(BMCR_SPEED1000 | BMCR_FULLDPLX);
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phy_modify(phydev, MII_BMCR, mask, 0);
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return qca83xx_suspend(phydev);
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}
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static struct phy_driver qca83xx_driver[] = {
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{
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/* QCA8337 */
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.phy_id = QCA8337_PHY_ID,
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.phy_id_mask = QCA8K_PHY_ID_MASK,
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.name = "Qualcomm Atheros 8337 internal PHY",
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/* PHY_GBIT_FEATURES */
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.probe = qca83xx_probe,
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.flags = PHY_IS_INTERNAL,
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.config_init = qca83xx_config_init,
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.soft_reset = genphy_soft_reset,
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.get_sset_count = qca83xx_get_sset_count,
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.get_strings = qca83xx_get_strings,
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.get_stats = qca83xx_get_stats,
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.suspend = qca8337_suspend,
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.resume = qca83xx_resume,
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}, {
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/* QCA8327-A from switch QCA8327-AL1A */
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.phy_id = QCA8327_A_PHY_ID,
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.phy_id_mask = QCA8K_PHY_ID_MASK,
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.name = "Qualcomm Atheros 8327-A internal PHY",
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/* PHY_GBIT_FEATURES */
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.link_change_notify = qca83xx_link_change_notify,
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.probe = qca83xx_probe,
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.flags = PHY_IS_INTERNAL,
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.config_init = qca8327_config_init,
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.soft_reset = genphy_soft_reset,
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.get_sset_count = qca83xx_get_sset_count,
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.get_strings = qca83xx_get_strings,
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.get_stats = qca83xx_get_stats,
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.suspend = qca8327_suspend,
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.resume = qca83xx_resume,
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}, {
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/* QCA8327-B from switch QCA8327-BL1A */
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.phy_id = QCA8327_B_PHY_ID,
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.phy_id_mask = QCA8K_PHY_ID_MASK,
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.name = "Qualcomm Atheros 8327-B internal PHY",
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/* PHY_GBIT_FEATURES */
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.link_change_notify = qca83xx_link_change_notify,
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.probe = qca83xx_probe,
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.flags = PHY_IS_INTERNAL,
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.config_init = qca8327_config_init,
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.soft_reset = genphy_soft_reset,
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.get_sset_count = qca83xx_get_sset_count,
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.get_strings = qca83xx_get_strings,
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.get_stats = qca83xx_get_stats,
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.suspend = qca8327_suspend,
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.resume = qca83xx_resume,
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}, };
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module_phy_driver(qca83xx_driver);
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static struct mdio_device_id __maybe_unused qca83xx_tbl[] = {
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{ PHY_ID_MATCH_EXACT(QCA8337_PHY_ID) },
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{ PHY_ID_MATCH_EXACT(QCA8327_A_PHY_ID) },
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{ PHY_ID_MATCH_EXACT(QCA8327_B_PHY_ID) },
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{ }
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};
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MODULE_DEVICE_TABLE(mdio, qca83xx_tbl);
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