da3d378dec
Let dma_fence::signaled, etc, read directly from the address that the hw is writing with updated completed fence seqno, so we can potentially notice that the fence is signaled sooner. Plus add some docs. Signed-off-by: Rob Clark <robdclark@chromium.org> Link: https://lore.kernel.org/r/20210726144359.2179302-2-robdclark@gmail.com Signed-off-by: Rob Clark <robdclark@chromium.org>
73 lines
1.6 KiB
C
73 lines
1.6 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2013 Red Hat
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* Author: Rob Clark <robdclark@gmail.com>
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*/
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#include "msm_ringbuffer.h"
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#include "msm_gpu.h"
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struct msm_ringbuffer *msm_ringbuffer_new(struct msm_gpu *gpu, int id,
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void *memptrs, uint64_t memptrs_iova)
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{
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struct msm_ringbuffer *ring;
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char name[32];
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int ret;
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/* We assume everwhere that MSM_GPU_RINGBUFFER_SZ is a power of 2 */
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BUILD_BUG_ON(!is_power_of_2(MSM_GPU_RINGBUFFER_SZ));
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ring = kzalloc(sizeof(*ring), GFP_KERNEL);
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if (!ring) {
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ret = -ENOMEM;
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goto fail;
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}
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ring->gpu = gpu;
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ring->id = id;
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ring->start = msm_gem_kernel_new(gpu->dev, MSM_GPU_RINGBUFFER_SZ,
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check_apriv(gpu, MSM_BO_WC | MSM_BO_GPU_READONLY),
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gpu->aspace, &ring->bo, &ring->iova);
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if (IS_ERR(ring->start)) {
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ret = PTR_ERR(ring->start);
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ring->start = 0;
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goto fail;
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}
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msm_gem_object_set_name(ring->bo, "ring%d", id);
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ring->end = ring->start + (MSM_GPU_RINGBUFFER_SZ >> 2);
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ring->next = ring->start;
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ring->cur = ring->start;
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ring->memptrs = memptrs;
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ring->memptrs_iova = memptrs_iova;
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INIT_LIST_HEAD(&ring->submits);
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spin_lock_init(&ring->submit_lock);
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spin_lock_init(&ring->preempt_lock);
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snprintf(name, sizeof(name), "gpu-ring-%d", ring->id);
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ring->fctx = msm_fence_context_alloc(gpu->dev, &ring->memptrs->fence, name);
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return ring;
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fail:
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msm_ringbuffer_destroy(ring);
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return ERR_PTR(ret);
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}
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void msm_ringbuffer_destroy(struct msm_ringbuffer *ring)
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{
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if (IS_ERR_OR_NULL(ring))
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return;
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msm_fence_context_free(ring->fctx);
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msm_gem_kernel_put(ring->bo, ring->gpu->aspace, false);
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kfree(ring);
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}
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